Stream Processor Architecture for Hard Real-Time Data Processing
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Solution Overview
Problem
Existing data stream processing technologies face challenges in meeting the high real-time performance requirements of ultra-high-bandwidth networks due to long stream processing cycles caused by read-modify-write latency, which is inadequate for hard real-time operations.
Innovation Solution
A stream processor architecture incorporating a FIFO memory and cache, where the FIFO receives and processes stream information, and the cache provides old data for the calculation unit, reducing the processing cycle from read-modify-write latency to modify latency by caching and bypassing external memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the stream processor accesses external memory to perform read-modify-write operations, then data storage reliability is improved, but the stream processing cycle becomes too long to meet hard real-time requirements
Solution Approach 1:
The patent segments the memory system into two distinct parts: a first memory (external memory) for reliable long-term data storage, and a second memory (on-chip memory) for fast temporary storage of old data. This segmentation allows the system to access frequently needed old data from the fast second memory without incurring the latency of external memory access, while still maintaining the reliability benefit of having data persisted in the first memory.
Solution Approach 2:
The system performs preliminary action by pre-loading old data into the second memory before it is needed for processing. The memory management unit proactively manages the second memory to ensure that when a stream processing operation needs to read old data, the data is already available in the fast second memory, eliminating the need for time-consuming external memory access during the critical processing path.
2Measurement precision
If the stream processor reads data from external memory before processing, then data accuracy is improved, but the processing speed decreases due to memory access latency
Solution Approach 1:
The patent applies local quality by creating a localized fast memory (second memory) specifically optimized for storing old data that is frequently accessed during stream processing. This local memory has different characteristics (higher speed) compared to the external first memory, and is positioned locally on the same chip as the processing unit to minimize access latency while maintaining data accuracy.
Solution Approach 2:
The second memory acts as an intermediary between the external first memory and the processing unit. Instead of the processing unit directly accessing external memory for every read operation, it accesses the intermediate second memory which already contains the required old data. This intermediary layer provides accurate data while eliminating the speed penalty of direct external memory access.
3Stability of the object's composition
If the stream processor waits for old data from external memory before processing current data, then data consistency is improved, but the stream processing latency increases
Solution Approach 1:
The system performs preliminary action by pre-fetching and storing old data in the second memory before processing operations require it. The memory management unit proactively manages this cache memory to ensure data is ready in advance, allowing processing to proceed immediately without waiting for external memory access while maintaining data consistency through proper cache management protocols.
Solution Approach 2:
The patent substitutes the mechanical external memory access system with a faster on-chip memory system for storing and retrieving old data. This replacement eliminates the physical access latency inherent in external memory systems while maintaining data consistency through appropriate cache coherence mechanisms and memory management.
4Device complexity
If the stream processor uses a simple queue structure for data buffering, then device complexity is reduced, but the stream processing throughput decreases due to sequential access limitations
Solution Approach 1:
The patent transitions from a one-dimensional sequential queue structure to a two-dimensional memory structure with direct random access capabilities. The second memory is organized as a cache memory with addressable locations that can be accessed in any order, enabling parallel processing of multiple data streams simultaneously while maintaining manageable complexity through standard memory management techniques.
Data Source
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AI summary
Embodiments of this application disclose a stream processor, to shorten a stream processing cycle of the stream processor and improve a capability of the stream processor to process a hard real-time service. According to the embodiments of this application, a method includes: a first in first out memory FIFO, a calculation unit, and a cache. The FIFO receives current stream information, where the current stream information carries a target stream number and target data; when the FIFO receives a read valid signal, the FIFO sends the target stream number and the target data to the calculation unit, and sends the target stream number to the cache; the cache obtains, based on the target stream number, old data that corresponds to the target stream number, and sends the old data that corresponds to the target stream number to the calculation unit; and the calculation unit performs, based on the target data, calculation on the old data that corresponds to the target stream number to obtain new data, and sends the new data to the cache.