Stream Processor Control Logic Partitioning via High-Level Synthesis
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Solution Overview
Problem
Existing stream processing systems face performance limitations due to inefficient optimization of control logic, which restricts the utilization of available hardware resources and leads to suboptimal throughput in pipelined parallel stream processors.
Innovation Solution
The method involves high-level synthesis to configure control logic for pipelined parallel stream processors by partitioning data paths into discrete regions, assigning discrete control logic elements, and using phase transition registers to align data across different clock phases, thereby optimizing hardware resource usage and timing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If control logic optimization is performed at the RTL stage using known arrangements, then the design complexity is reduced, but the hardware resource utilization and timing speed achieve only suboptimal results
Solution Approach 1:
The data path is partitioned into multiple discrete regions, and control logic is assigned to each region independently. This segmentation enables localized optimization of control logic while maintaining overall system throughput, resolving the contradiction between productivity improvement and complexity management
Solution Approach 2:
The invention performs control logic optimization at the high-level synthesis stage rather than at the RTL stage, adding a temporal dimension to the optimization process. This early-stage optimization enables better hardware resource utilization and timing performance without being constrained by later-stage design complexities
2Productivity
If the data path is partitioned into multiple discrete regions with separate control logic, then hardware resource utilization is optimized, but the device complexity increases
Solution Approach 1:
The data path is divided into discrete regions with control logic assigned to each region. This segmentation allows independent optimization of control logic for each region, improving hardware resource utilization while managing complexity through modular design
Solution Approach 2:
Different control logic elements are assigned to different regions of the data path based on local requirements. This local quality approach optimizes control logic placement and resource allocation for each specific region, achieving better overall hardware utilization without uniform complexity across the entire system
Data Source
AI summary
A method of utilizing high level synthesis to automatically configure control logic of a hardware design for a pipelined parallel stream processor includes obtaining a scheduled graph representing a processing operation in the time domain as a function of clock cycles. The graph includes a data path to be implemented in hardware as part of the stream processor, an input, an output, functional objects, and parallel branches to enable data values to be streamed therethrough from the input to the output as a function of increasing clock cycle. The functional objects are grouped based upon having a cycle position dependent upon common factors. Common control logic elements are allocated to groups of functional objects. The graph and allocated control logic is used to define a hardware design for the pipelined parallel stream processor.