Parallel Stream Processor Data Path Optimization
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Solution Overview
Problem
Existing methods struggle to determine appropriate scaling factors, maximum values, and rounding methods for each stage of a calculation in a parallel stream processor, balancing on-chip resource consumption with precision and accuracy, especially in fixed-point arithmetic where errors from underflow and overflow can occur.
Innovation Solution
A method is developed to generate a hardware design for a pipelined parallel stream processor by defining processing operations, specifying propagation rules, and optimizing the number of bits, offset, format, and rounding mode for each discrete object in the data path to create an optimized graph that minimizes hardware requirements while ensuring sufficient precision and range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If fixed-point arithmetic is used in parallel stream processor to reduce hardware resource consumption, then logic area is reduced, but precision and accuracy may be compromised due to underflow and overflow errors
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the number of bits, offset, number format, and rounding mode for each discrete object in the data path. This allows the system to optimize precision for each calculation stage while maintaining fixed-point arithmetic efficiency, resolving the contradiction between reduced logic area and maintained precision through automated type optimization.
2Measurement precision
If manual specification of scaling factors and rounding methods is performed for each calculation stage, then precision can be maintained, but device complexity and manual specification burden increase
Solution Approach 1:
The patent implements self-service through automated type optimization that automatically determines appropriate types and propagation rules for each discrete object in the data path. The system propagates precision requirements through the calculation graph and automatically selects optimal parameters without manual intervention, reducing device complexity while maintaining precision through self-optimizing algorithms.
Solution Approach 2:
The patent applies preliminary action by performing automated type optimization during the design phase before hardware implementation. The system pre-determines optimal scaling factors, bit widths, and rounding modes for each calculation stage by analyzing the computation graph, eliminating the need for complex manual specification during operation while ensuring precision requirements are met.
3Measurement precision
If more bits are allocated to each discrete object in the data path, then precision is improved, but hardware resource consumption increases
Solution Approach 1:
The patent applies local quality by optimizing the number of bits, offset, and format parameters individually for each discrete object in the data path based on its specific precision requirements. Rather than uniformly allocating bits across all objects, the system determines the minimum necessary precision for each calculation stage, reducing total hardware resource consumption while maintaining adequate precision locally where needed.
Data Source
AI summary
A method of generating a hardware design for a pipelined parallel stream processor, by defining a hardware processing operation; specifying at least one propagation rule; defining a graph representing the processing operation in the time domain, comprising at least one data path to be implemented as a hardware design and a plurality of parallel branches; each data path having: at least one data path input, output, and discrete object corresponding to a hardware element; each discrete object comprises an input for receiving an input variable, an operator for executing a function on said input variable, and an output variable; optimizing each output from each discrete object in dependence upon the propagation rule to produce an optimised graph; and utilizing the optimised graph to define an optimised hardware design for implementation in said pipelined parallel stream processor.