Pipelined Stream Processor Dedicated Logic Units Prevent Data Collision

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Solution Overview

Problem

Statically scheduled pipelined stream processors face inefficiencies when handling a large number of small data sets, leading to stalling and increased latency due to the need for flushing and buffer management, which affects the processing of multiple data sets concurrently.

Innovation Solution

Implementing dedicated logic units to control the progress of each data set through the pipeline, allowing non-overlapping sections and maintaining efficient data flow by monitoring fill and flush levels, thereby avoiding collisions and stalling, and enabling concurrent processing of multiple data sets.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single pipeline processes multiple data sets concurrently using static scheduling, then device complexity is reduced, but data collision and stalling occur increasing latency

Engineering Contradiction:
Improvepipeline structureVSAvoidlatency
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The pipeline is segmented into multiple lanes, with each lane dedicated to processing a specific data set. This segmentation prevents data collision by providing separate processing paths while maintaining the benefits of a pipelined architecture. Each lane operates independently, allowing concurrent processing of multiple data sets without stalling.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically allocates pipeline resources by creating multiple lanes that can be activated based on data set requirements. The dynamic lane allocation allows the pipeline to adapt to varying data set sizes and processing requirements, optimizing throughput while preventing data collision through spatial separation.

Inventive Principle:
Principle #15Dynamics

2Productivity

If buffer space is increased to handle multiple small data sets, then data flow efficiency improves, but device complexity and resource usage increase

Engineering Contradiction:
Improvedata flow efficiencyVSAvoidbuffer management
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Buffers are segmented into lane-specific portions, with each lane having its own buffer space. This segmentation eliminates the need for complex centralized buffer management while improving data flow efficiency within each lane. The segmented buffer structure allows independent access and management, reducing overhead and complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each pipeline lane operates autonomously with its own buffer management, eliminating the need for centralized control. The self-service approach allows each lane to manage its own data flow independently, reducing overall system complexity while maintaining high productivity through parallel operation.

Inventive Principle:
Principle #25Self-service

3Reliability

If pipeline flushing is implemented between data sets, then data collision is prevented, but processing latency increases

Engineering Contradiction:
Improvedata separationVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The pipeline is divided into multiple lanes that provide natural data separation without requiring flushing operations. Each lane processes its assigned data set independently, preventing data collision through spatial separation rather than temporal flushing. This eliminates the latency penalty associated with pipeline flushing while maintaining data integrity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Data sets are pre-assigned to specific lanes before entering the pipeline, establishing clear boundaries and preventing collision before it can occur. This preliminary assignment eliminates the need for reactive flushing operations, allowing continuous processing without interruptions or latency penalties.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9514094B2Processing data sets using dedicated logic units to prevent data collision in a pipelined stream processor
Publication Date: 2016.12.06 GROQ UK LTD
  • US9514094B2 patent drawing
  • US9514094B2 patent drawing
  • US9514094B2 patent drawing

AI summary

There is provided a method for processing multiple sets of data concurrently in a statically scheduled pipelined stream processor by allowing a data set to enter the pipeline while another data set is being processed. Dedicated logic units enable independent control of each of the data sets being processed.