Hardware Stream Processor Interconnect Optimization for FPGA Resources
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Solution Overview
Problem
The design of hardware stream processors for FPGAs faces challenges in optimizing hardware resources for efficient data transfer between interconnected processes, including flow control, clock rates, data widths, and preventing deadlocks, which often requires manual optimization and can be error-prone and wasteful of resources.
Innovation Solution
A method for automatically generating an optimized hardware stream processor design by optimizing parameters such as flow control methodologies, clock rates, data widths, and latency scheduling between processes, minimizing hardware requirements while ensuring required functionality, and automatically inserting necessary logic and buffers to prevent deadlocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual optimization is used for hardware resources, then design flexibility is maintained, but operator error increases and optimization efficiency decreases
Solution Approach 1:
The system performs automatic optimization of hardware resources without requiring manual intervention. The optimization module autonomously analyzes the process network, determines optimal FIFO buffer sizes, and generates optimized hardware designs, allowing the system to serve itself rather than relying on external operator input.
Solution Approach 2:
The patent replaces manual mechanical optimization processes with an automated computational system. The optimization module uses algorithms to automatically determine hardware parameters, substituting the mechanical process of manual analysis and adjustment with an automated electronic design automation (EDA) based approach.
2Productivity
If more hardware resources are allocated for interconnect, then data transfer efficiency improves, but available resources for compute operations decrease
Solution Approach 1:
The system automatically determines optimal parameters for FIFO buffers and interconnect resources based on the specific requirements of the process network. By dynamically adjusting buffer sizes and interconnect configurations to match actual data flow needs, the system achieves efficient data transfer while minimizing resource consumption, leaving more resources available for compute operations.
Solution Approach 2:
The optimization module allocates hardware resources for interconnect and buffering on a needs-based basis rather than providing maximum resources everywhere. It identifies where minimal buffering is sufficient and where larger buffers are necessary, avoiding excessive resource allocation in areas where it would not improve performance.
3Reliability
If FIFO buffer sizes are increased to prevent deadlocks, then system reliability improves, but hardware resource consumption increases
Solution Approach 1:
The optimization module performs preliminary analysis of the process network to identify potential deadlock scenarios before generating the hardware design. By proactively determining appropriate FIFO buffer sizes during the design phase rather than adding excessive buffers as a precaution, the system prevents deadlocks while minimizing resource consumption.
Solution Approach 2:
The system applies different FIFO buffer sizes to different interconnect paths based on their specific requirements. Rather than uniformly increasing buffer sizes throughout the system, the optimization module identifies specific paths where larger buffers are necessary to prevent deadlocks and allocates resources locally where needed, maintaining overall system reliability while minimizing total resource consumption.
Data Source
AI summary
Embodiments of the invention provide a method of automatically generating a hardware stream processor design including plural processes and interconnect between the plural processes to provide data paths between the plural processes, the method comprising: providing an input designating processes to be performed by the stream processor; automatically optimizing parameters associated with the interconnect between processes within the design so as to minimise hardware requirements whilst providing the required functionality; and generating an optimized design in accordance with the optimization.