Stream Scheduling Optimization in Pipelined Stream Processors
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Solution Overview
Problem
Current methods for optimizing data paths in pipelined hardware, such as FPGAs, are inefficient in utilizing resources due to suboptimal scheduling and excessive buffering, which limits the number of data paths and kernels that can be implemented, leading to reduced processing power.
Innovation Solution
The method employs integer linear programming to minimize buffering by optimizing the arrangement of nodes and edges in a graph representation of the data path, using stream offsets and tapping/folding buffers to reduce memory usage and improve resource allocation, thereby creating an efficient schedule that minimizes total buffering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional scheduling methods are used in pipelined hardware, then implementation is simpler, but resource utilization is inefficient due to excessive buffering
Solution Approach 1:
The patent transforms the scheduling problem from a traditional time-based approach to a mathematical optimization problem by changing parameters to node execution times and buffer sizes. Integer linear programming is used to optimize these parameters, minimizing total buffer size while satisfying data dependency constraints, thereby improving resource utilization without excessive complexity
Solution Approach 2:
The patent introduces an intermediary optimization layer between the data path graph and the physical hardware implementation. This intermediary uses mathematical modeling to determine optimal buffer placements and sizes, acting as a mediator that translates logical data dependencies into efficient physical resource allocation
2Productivity
If more data paths and kernels are implemented in the FPGA, then processing power increases, but the number of available resources decreases due to fixed block RAM
Solution Approach 1:
The patent merges multiple buffer instances into shared buffer resources by identifying common data dependencies across different data paths. The optimization algorithm determines which buffers can be shared and calculates optimal shared buffer sizes, effectively combining previously separate memory allocations into unified resources that serve multiple kernels simultaneously
Solution Approach 2:
The optimized scheduling approach enables buffers to serve multiple functions and multiple data paths. A single buffer can be shared across different kernels and data paths at different time intervals, making the block RAM resources universal rather than dedicated to specific functions, thereby increasing the number of implementable data paths
3Reliability
If buffering is increased to handle data dependencies, then data path correctness is maintained, but memory usage increases reducing the number of implementable kernels
Solution Approach 1:
The patent performs preliminary optimization of buffer allocations before hardware implementation by solving the integer linear programming problem during the design phase. This preliminary action determines the minimal sufficient buffering required for each data dependency, preventing over-provisioning of memory resources while ensuring data correctness is maintained
Data Source
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AI summary
There is provided a method of generating a hardware design for a pipelined parallel stream processor. The method comprises defining, on a computing device, a processing operation designating processes to be implemented in hardware as part of said pipelined parallel stream processor; defining, on a computing device, a graph representing said processing operation as a parallel structure in the time domain as a function of clock cycles, said graph comprising at least one data path to be implemented as a hardware design for said pipelined parallel stream processor and comprising a plurality of branches configured to enable data values to be streamed therethrough, the branches of the or each data path being represented as comprising at least one input, at least one output, at least one discrete object corresponding directly to a hardware element to be implemented in hardware as part of said pipelined parallel stream processor, the or each discrete object being operable to execute a function for one or more clock cycles and having a predefined latency associated therewith, said predefined latency representing the time required for said hardware element to execute said function; , said data values propagating through said data path from the at least one input to the at least one output as a function of increasing clock cycle; defining, on a computing device, the at least one data path and associated latencies of said graph as a set of algebraic linear inequalities; solving, on a computing device, said set of linear inequalities; optimising, on a computing device, the at least one data path in said graph using said solved linear inequalities to produce an optimised graph; and utilising, on a computing device, said optimised graph to define an optimised hardware design for implementation in hardware as said pipelined parallel stream processor.