Streaming Chip Data Flow Control via Count Signals
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In streaming architecture chips, traditional data flow control using valid and ready handshake signals leads to a scattered ready signal, complicating circuit routing and timing closure due to the need for one ready signal to drive multiple register circuits, making efficient data transfer and processing inefficient.
Innovation Solution
A data flow control device with first and second data buffer modules and operation modules, where the second data buffer module sends a flow control count signal to the first data buffer module to inform it of the amount of data that can be received, allowing the first data buffer module to send data signals and valid signals in a specific sequence, thereby eliminating the need for real-time ready signal detection and reducing signal scattering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If one ready signal is used to connect to many modules and drive many register circuits to ensure synchronous operation, then the functional modules can work together efficiently, but the ready signal is scattered too much and the circuit routing becomes complicated, making timing closure difficult
Solution Approach 1:
The patent segments the flow control mechanism by introducing separate flow control signals (fc_valid, fc_ready) independent from the data transfer signals (valid, ready). This segmentation allows the ready signal to be localized to specific buffer modules rather than being scattered across multiple modules, thereby simplifying circuit routing while maintaining efficient data transfer coordination.
Solution Approach 2:
The patent introduces flow control signals as intermediary elements between upstream and downstream modules. These flow control signals act as mediators that coordinate data transfer without requiring the ready signal to be directly connected to all modules, thus reducing signal scattering and simplifying routing while enabling efficient synchronous operation.
2Reliability
If traditional valid and ready handshake signals are used for data flow control, then data transfer can be coordinated between modules, but the ready signal scattering causes complicated circuit routing and timing closure difficulties
Solution Approach 1:
The patent segments the handshake protocol into independent flow control signals (fc_valid, fc_ready) and data transfer signals (valid, ready). This segmentation allows reliable data flow control to be maintained while the flow control signals can be routed independently, simplifying timing closure without compromising reliability.
Solution Approach 2:
The patent changes the parameters of the flow control mechanism by introducing separate flow control signal pairs that operate independently from the data transfer signals. This parameter change allows the system to maintain reliable coordination while reducing the complexity of signal routing and timing closure through localized signal management.
3Productivity
If multiple modules are connected in series with shared ready signals to ensure synchronous operation, then efficient data processing can be achieved, but the signal scattering makes the circuit routing complicated
Solution Approach 1:
The patent segments the signal distribution by assigning dedicated flow control signals to each buffer module in the series connection. This segmentation allows each module to operate synchronously for efficient data processing while the localized signal connections simplify circuit routing compared to a shared ready signal approach.
Solution Approach 2:
The patent introduces flow control signals as intermediaries that mediate the synchronization between series-connected modules. These intermediaries enable efficient data processing through coordinated operation while avoiding the signal scattering problem by providing localized, dedicated control signals for each module interface.
Data Source
AI summary
A data flow control device in a streaming architecture chip includes at least one first data buffer module, at least one operation module and at least one second data buffer module. The second data buffer module is configured to send a flow control count signal to the first data buffer module, the flow control count signal being used for informing the first data buffer module of an amount of data that can be received of the second data buffer module. The first data buffer module is configured to send a data signal and a valid signal to the second data buffer module via the operation modules according to the flow control count signal, the valid signal being used for indicating that a corresponding data signal is valid.