Streaming Editor Circuit for Packet Deparsing
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Solution Overview
Problem
Current data packet processing systems require extensive hardware resources and high latency due to the need to extract and reconstruct all packet headers for editing, especially when only a few headers need to be modified, leading to inefficiencies in header editing operations.
Innovation Solution
An integrated circuit with a pipelined operation circuit and a state machine that performs editing operations on data packets with a stack of headers and a data payload, allowing for selective editing of headers without extracting all headers, thereby reducing hardware resource usage and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If all packet headers are extracted and reconstructed for editing, then header editing can be performed, but hardware resources increase and latency increases
Solution Approach 1:
The patent extracts only the specific header fields that need to be edited from the packet, rather than extracting and reconstructing all headers. This selective extraction approach reduces hardware resource requirements while maintaining the necessary header editing capability.
Solution Approach 2:
The patent segments the header editing process into independent field-level operations. Each header field can be edited separately using dedicated circuitry, allowing parallel processing of multiple fields without requiring complete header extraction and reconstruction, thus reducing overall hardware complexity.
2Ease of operation
If all packet headers are extracted and reconstructed for editing, then header editing can be performed, but latency increases
Solution Approach 1:
The patent performs preliminary identification of which header fields need editing before the actual editing operation. This allows the system to prepare only the necessary field extraction and editing circuitry in advance, avoiding the time-consuming process of extracting and reconstructing entire headers during the critical editing phase.
Solution Approach 2:
By extracting only the specific header fields that require editing rather than all headers, the patent significantly reduces the amount of data that needs to be processed, buffered, and reconstructed, thereby minimizing processing latency while maintaining full header editing capability.
3Device complexity
If selective header editing is implemented, then hardware resources are reduced, but header editing capability may be limited
Solution Approach 1:
The patent implements universal header field editing circuitry that can operate on any header field within the packet structure. The same editing logic and circuitry can be applied to different header fields by configuring the field selection inputs, providing adaptability across various header types without requiring dedicated hardware for each specific field.
Solution Approach 2:
The patent uses dynamically configurable field selection mechanisms that allow the editing circuitry to adapt to different header structures and editing requirements. The field identifiers and selection logic can be programmed or configured at runtime, enabling the same hardware resources to handle diverse header editing scenarios flexibly.
Data Source
AI summary
Apparatus and associated methods relating to data packet deparsing include an editing circuit configured to perform one or more predetermined editing operations on headers of an incoming data packet step by step without extracting all headers from the incoming data packet. In an illustrative example, an editor circuit may include an updating circuit configured to receive the data packet and update a header in the data packet. The editor circuit may also include a removal circuit configured to remove a header from the data packet. The editor circuit may also include an insertion circuit configured to insert one or more consecutive headers to the data packet. A state machine may be configured to enable or disable the updating circuit, the removal circuit, and/or the insertion circuit based on the predetermined editing operations. By using the editing circuit, packet deparsing may be performed with less hardware resources and low latency.