Streaming Engine Micro-TLB for Dual Address Translation
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Solution Overview
Problem
Modern digital signal processors face challenges with increasing workloads, memory bandwidth, and latency issues, particularly in real-time data processing, where memory access and scheduling are complex due to growing system complexity and unreliable memories.
Innovation Solution
A streaming engine is introduced that includes an address generator and a stream head register to manage data streams, utilizing an address translation unit for virtual to physical address translation, allowing for efficient sequential data access and minimizing cache misses by bypassing the level one data cache.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional memory access methods are used in real-time data processing, then system complexity increases and memory latency worsens, but memory bandwidth and processing efficiency are limited
Solution Approach 1:
The patent extracts the address translation function from the general memory access path and implements it specifically in the streaming engine's micro-TLB. This dedicated address translation unit handles sequential address translations independently, removing the bottleneck of general-purpose memory management and reducing system complexity for real-time data processing workloads.
Solution Approach 2:
The memory address space is segmented into manageable pages with dedicated translation entries in the micro-TLB. By dividing the address translation task into page-level segments and caching them locally, the system achieves efficient sequential access without requiring complex global memory management, thus improving productivity while controlling device complexity.
2Measurement precision
If address translation is performed for every memory access, then address translation accuracy is maintained, but memory access time increases
Solution Approach 1:
The micro-TLB performs address translation in advance by caching page table entries before they are needed for actual data access. When sequential addresses are accessed, their translations are pre-computed and stored, allowing immediate data retrieval without repeated translation operations, thus maintaining accuracy while reducing access time.
Solution Approach 2:
Instead of performing full address translation for every memory access, the patent creates copies of translation entries (page table mappings) and stores them locally in the micro-TLB. This copying mechanism allows the streaming engine to use cached translations repeatedly for sequential accesses, ensuring translation accuracy is maintained while dramatically reducing memory access time.
3Speed
If level one data cache is used for data access, then data access speed is improved, but cache misses increase and bandwidth is consumed
Solution Approach 1:
The patent introduces a micro-TLB as an intermediary component between the streaming engine and the memory system. This intermediary handles address translation and enables direct access to data without requiring L1 cache intermediation, thereby maintaining high data access speed while reducing cache miss rates and conserving memory bandwidth for essential operations.
Data Source
AI summary
A streaming engine employed in a digital data processor specifies a fixed read only data stream. An address generator produces virtual addresses of data elements. An address translation unit converts these virtual addresses to physical addresses by comparing the most significant bits of a next address N with the virtual address bits of each entry in an address translation table. Upon a match, the translated address is the physical address bits of the matching entry and the least significant bits of address N. The address translation unit can generate two translated addresses. If the most significant bits of address N+1 match those of address N, the same physical address bits are used for translation of address N+1. The sequential nature of the data stream increases the probability that consecutive addresses match the same address translation entry and can use this technique.