Streaming Engine Prefetching for Parity Fault Recovery

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Solution Overview

Problem

Modern digital signal processors face challenges with increasing workloads, memory bandwidth and scheduling issues, memory system latency, and memory reliability, particularly in real-time data processing applications like video encoding, where memory accesses are difficult to achieve within available resources.

Innovation Solution

A streaming engine is employed in a digital signal processor that fetches data streams ahead of use by the central processing unit core, utilizing an address generator and parity checks to ensure data integrity, with the ability to restart fetching upon parity faults.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data is fetched from memory in real-time processing, then memory bandwidth is improved, but memory reliability deteriorates due to increased access complexity and latency

Engineering Contradiction:
Improvememory bandwidthVSAvoidmemory reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The streaming engine pre-fetches data from memory into an internal buffer before the processor core needs it, performing the memory access operation in advance. This preliminary action increases memory bandwidth utilization while isolating the processor from memory latency and reliability issues, as the processor interacts only with the reliable internal buffer.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The streaming engine acts as an intermediary component between memory and the processor core. It includes an address generator and data buffer that mediate memory access operations, generating addresses and fetching data according to stream parameters while providing error detection and correction capabilities, thus improving both bandwidth and reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If parity checks are performed on fetched data, then data integrity is improved, but processing time increases due to additional verification steps

Engineering Contradiction:
Improvedata integrityVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

Parity bits are calculated and stored with the data during the pre-fetch operation, before the processor needs the data. This preliminary computation of error detection codes allows for rapid verification when data is retrieved, ensuring data integrity without adding significant processing time at the point of use.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The parity check operation is performed continuously in the background as data is fetched and buffered, rather than being a separate blocking operation. The streaming engine maintains the data stream flow while simultaneously performing error detection, so the processor receives verified data without interruption to the overall processing timeline.

Inventive Principle:
Principle #20Continuity of useful action

3Reliability

If the streaming engine restarts fetching upon parity faults, then reliability is improved through error recovery, but productivity decreases due to restart overhead

Engineering Contradiction:
Improveerror recoveryVSAvoidprocessing throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The streaming engine implements a feedback mechanism where parity check results are monitored and used to control restart behavior. When a parity fault is detected, the engine automatically restarts fetching from the problematic address, providing error recovery. The feedback loop is designed to minimize restart overhead by only triggering restarts when actually needed, thus maintaining high productivity while improving reliability.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12450120B2Streaming engine with error detection, correction and restart
Publication Date: 2025.10.21 TEXAS INSTRUMENTS INC
  • US12450120B2 patent drawing
  • US12450120B2 patent drawing
  • US12450120B2 patent drawing

AI summary

Disclosed embodiments relate to a streaming engine employed in, for example, a digital signal processor. A fixed data stream sequence including plural nested loops is specified by a control register. The streaming engine includes an address generator producing addresses of data elements and a steam head register storing data elements next to be supplied as operands. The streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer. Parity bits are formed upon storage of data in the stream buffer which are stored with the corresponding data. Upon transfer to the stream head register a second parity is calculated and compared with the stored parity. The streaming engine signals a parity fault if the parities do not match. The streaming engine preferably restarts fetching the data stream at the data element generating a parity fault.