Streaming Engine Address Translation Using One TLB Read for Two Addresses
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Solution Overview
Problem
Modern digital signal processors face challenges with increasing workloads, memory latency, and unreliable memory and registers, which impact real-time data processing and memory access efficiency, particularly in video encoding applications.
Innovation Solution
A streaming engine with an address generator and translation unit for virtual to physical address translation, enabling efficient data streaming and address management, particularly for real-time filtering operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional address translation methods are used, then address translation functionality is provided, but memory access efficiency deteriorates and bandwidth is insufficient
Solution Approach 1:
The address translation unit is segmented to process multiple address translation operations in parallel. The unit divides the address translation task into simultaneous operations, allowing multiple virtual addresses to be translated to physical addresses concurrently, thereby improving memory access efficiency and reducing latency without requiring sequential processing
Solution Approach 2:
The address translation unit performs preliminary address translation before memory access requests are fully processed. By pre-translating virtual addresses to physical addresses in advance, the system reduces the time required during actual memory access operations, improving overall productivity and reducing memory latency
2Productivity
If more address translation resources are allocated, then address translation capability is improved, but device complexity increases
Solution Approach 1:
The address translation unit is designed with multi-functionality to handle various address translation scenarios using a single integrated structure. It can translate addresses for different data streams, support multiple virtual memory spaces, and perform both address translation and validation functions, thereby increasing bandwidth without proportionally increasing device complexity
Solution Approach 2:
The address translation unit merges address translation functionality with the streaming engine's address generation capabilities. By combining these functions into a unified structure, the system achieves improved address translation capability and bandwidth while avoiding the complexity overhead of separate dedicated translation hardware for each function
Data Source
AI summary
A streaming engine employed in a digital data processor specifies a fixed read only data stream. An address generator produces virtual addresses of data elements. An address translation unit converts these virtual addresses to physical addresses by comparing the most significant bits of a next address N with the virtual address bits of each entry in an address translation table. Upon a match, the translated address is the physical address bits of the matching entry and the least significant bits of address N. The address translation unit can generate two translated addresses. If the most significant bits of address N+1 match those of address N, the same physical address bits are used for translation of address N+1. The sequential nature of the data stream increases the probability that consecutive addresses match the same address translation entry and can use this technique.