Stress Balance Layer for Compound Semiconductor Wafer Distortion
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Solution Overview
Problem
Compound semiconductor wafers experience significant stress and distortion during the formation of integrated circuits, particularly for larger diameters, leading to bowing and cracking issues, and conventional stress balance structures are inadequate for these wafers, especially when heat dissipation is required.
Innovation Solution
A structure comprising a contact metal layer and at least one stress balance layer with high thermal conductivity (>10 W/m-K) is formed on the bottom surface of the compound semiconductor wafer, with the stress balance layer made from materials like AlN, SiC, or Ti, and deposited using methods such as sputtering or CVD, to balance stress and facilitate heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a stress balance layer is formed on the bottom surface of a compound semiconductor wafer, then the stress suffered by the wafer is balanced and distortion is reduced, but the heat dissipation capability is insufficient
Solution Approach 1:
The stress balance layer is designed to perform dual functions: balancing stress to reduce wafer distortion and dissipating heat from high-power devices. By selecting materials with appropriate mechanical and thermal properties, the single layer simultaneously addresses both stress stability and temperature management requirements.
Solution Approach 2:
The patent specifies that the stress balance layer must have a thermal conductivity greater than 10 W/m-K, which is a significant parameter change from conventional stress balance layers. This elevated thermal conductivity threshold ensures the layer can effectively dissipate heat while maintaining its stress balancing function.
2Area of stationary object
If the compound semiconductor wafer diameter is increased to 3 inches or larger, then the device performance is enhanced, but the bowing distortion and cracking become much more significant
Solution Approach 1:
The stress balance layer acts as a counterbalancing element on the bottom surface of the wafer, opposing the stress accumulation that occurs during integrated circuit formation. This counter-stress mechanism prevents bowing distortion and edge cracking that would otherwise occur in large-diameter wafers.
Solution Approach 2:
The stress balance layer is formed on the bottom surface before the wafer undergoes thinning or high-power device operation. This preliminary stress balancing prevents distortion from developing during subsequent processing and operation, particularly important for large-diameter wafers where distortion effects are magnified.
3Length of moving object
If the compound semiconductor wafer is thinned to improve device performance, then the heat dissipation becomes more difficult and stress balancing becomes more challenging, but the distortion and cracking increase
Solution Approach 1:
The stress balance layer with high thermal conductivity serves as an intermediary between the thinned compound semiconductor wafer and the underlying substrate or heat sink. It facilitates heat transfer from the thin wafer structure while simultaneously providing mechanical support to prevent distortion and cracking that would otherwise occur in thinned wafers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure effectively reduces wafer distortion and provides both stress balance and heat dissipation capabilities, enhancing the performance of compound semiconductor devices, especially for high-power applications.
Implementation Method 1
The stress suffered by the compound semiconductor wafer is balanced by the at least one stress balance layer, so that the distortion of the compound semiconductor wafer is reduced
Implementation Method 2
a thermal conductivity of the at least one stress balance layer is greater than or equal to 10 W/m-K... the heat can be dissipated through the bottom of the compound semiconductor wafer to a package substrate
Data Source
AI summary
An improved structure for reducing compound semiconductor wafer distortion comprises a contact metal layer and at least one stress balance layer. The contact metal layer is formed on a bottom surface of a compound semiconductor wafer; the at least one stress balance layer is formed on a bottom surface of the contact metal layer, wherein a thermal conductivity of the at least one stress balance layer is greater than or equal to 10 W/m-K. The stress suffered by the compound semiconductor wafer is balanced by the at least one stress balance layer, so that the distortion of the compound semiconductor wafer is reduced.