Stress-Balancing Layer for Electronic Package Warpage Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional chip scale packaging methods experience warpage due to thermal expansion mismatch between the encapsulant and dielectric layers, leading to poor planarity, reliability issues, and increased production defects.
Innovation Solution
A stress-balancing layer is formed on the packaging layer's second surface, with a coefficient of thermal expansion different from the packaging layer, to balance stress and reduce warpage, integrated with the packaging layer or encapsulating layer, and bonded to the electronic component.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional chip scale packaging is manufactured without a stress-balancing layer, then the manufacturing process is simple, but warpage occurs due to CTE mismatch between encapsulant and dielectric layers
Solution Approach 1:
A stress-balancing layer is introduced as an intermediary component between the encapsulant and the external environment. This layer has a coefficient of thermal expansion specifically selected to balance the CTE mismatch between the encapsulant and dielectric layers, thereby preventing warpage without significantly complicating the manufacturing process
Solution Approach 2:
The packaging structure is designed as a composite system comprising multiple layers with different material properties. The stress-balancing layer is made of a material whose CTE is engineered to compensate for the CTE difference between the encapsulant and dielectric layers, creating a balanced composite structure that maintains planarity
2Reliability
If high temperature manufacturing process is used, then encapsulant curing is effective, but CTE mismatch causes semiconductor elements to bend and creates warpage
Solution Approach 1:
The stress-balancing layer is designed to preemptively counteract the warpage forces that will arise during high-temperature curing. By selecting a material with appropriate CTE properties, the layer creates a compensating stress that balances the expansion forces during the curing process, preventing semiconductor element bending
Solution Approach 2:
The coefficient of thermal expansion of the stress-balancing layer is specifically selected and controlled as a key parameter. This parameter is chosen to mathematically balance the CTE mismatch between encapsulant and dielectric layers, ensuring that the net thermal stress during high-temperature processing is minimized
3Productivity
If large degree of warpage occurs, then manufacturing process continues, but electrical connections are degraded and production yield decreases
Solution Approach 1:
The stress-balancing layer provides beforehand cushioning by preventing warpage before it can occur. This protective measure ensures that electrical connections remain intact throughout the manufacturing process, avoiding yield losses from connection failures while maintaining production continuity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The stress-balancing layer effectively reduces warpage, enhances the reliability of electrical connections, and increases production yield by maintaining structural integrity and preventing fragmentation.
Implementation Method 1
since the encapsulant 13 and the dielectric layer 140 of the circuit structure 14 have quite different coefficients of thermal expansion (CTEs), CTE mismatch occurs
Data Source
AI summary
The disclosure provides an electronic package and a method of manufacturing the same. The method is characterized by encapsulating an electronic component with a packaging layer and forming on an upper surface of the packaging layer a circuit structure that is electrically connected to the electronic component; and forming a stress-balancing layer on a portion of the lower surface of the packaging layer to balance the stress exerted on the upper and lower surfaces of the packaging layer, thereby reducing the overall package warpage and facilitating the manufacturing process.