Stress Compensation Control Circuit for Semiconductor Sensors
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Solution Overview
Problem
Existing stress compensation methods for semiconductor sensors, such as those using diffusion resistance, suffer from increased compensation errors at high temperatures due to substrate leak current variations and require larger chip areas for accurate resistance value formation, limiting their ability to maintain detection sensitivity accuracy across temperature ranges.
Innovation Solution
A stress compensation control circuit utilizing depletion and enhancement transistors with orthogonal channel directions to generate a stress compensation voltage, adjusting the detection sensitivity of semiconductor sensors by synthesizing compensation currents based on transconductance changes, thereby reducing chip area and maintaining accuracy similar to room temperature conditions across a wide temperature range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If diffusion resistance is used for stress compensation, then stress compensation is achieved, but substrate leak current increases and compensation error increases at high temperatures
Solution Approach 1:
The patent changes the type of transistor used for stress compensation from diffusion resistance to MOS transistors (depletion and enhancement types), altering the physical parameters of the compensation mechanism to eliminate temperature-dependent leak current while maintaining stress compensation accuracy
Solution Approach 2:
The patent combines depletion transistors and enhancement transistors in a composite configuration to achieve stress compensation. This composite structure leverages the complementary characteristics of the two transistor types to cancel out temperature effects while maintaining accurate stress compensation
2Measurement precision
If diffusion resistance is used for stress compensation, then stress compensation is achieved, but chip area increases
Solution Approach 1:
The patent changes from using large-area diffusion resistance structures to compact MOS transistor structures, significantly reducing the area required for stress compensation while maintaining or improving compensation accuracy
Solution Approach 2:
The patent uses transistor geometries that can be precisely replicated through standard semiconductor fabrication processes, allowing accurate stress compensation with minimal area overhead compared to diffusion resistance methods
3Reliability
If MOS transistors with orthogonal channel directions are used, then temperature-independent compensation is achieved, but device complexity increases
Solution Approach 1:
The patent employs asymmetric orientation of transistor channel directions (orthogonal arrangements) to exploit the anisotropic piezoresistive effects of MOS transistors. This asymmetric configuration enables temperature-independent stress compensation by balancing directional stress responses
Solution Approach 2:
The patent designs the MOS transistor configuration to simultaneously provide stress compensation and temperature compensation functions. The orthogonal channel arrangement allows the same structure to respond to both mechanical stress and thermal effects, eliminating the need for separate compensation circuits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively compensates for detection sensitivity changes due to stress, achieving high accuracy without substrate leak current issues and reducing chip area requirements, even at elevated temperatures.
Implementation Method 1
the detection sensitivity of the Hall element with respect to the strength of the magnetic field changes due to a piezo effect
Data Source
AI summary
A stress compensation control circuit of the present invention is provided which is capable of using a compensation error similar to that at room temperature even at a high temperature and reducing the area of a chip for a semiconductor sensor as compared with the related art. The stress compensation control circuit compensates for a change in detection sensitivity due to a stress to be applied to the semiconductor sensor. The stress compensation control circuit includes a stress compensation voltage generating circuit generating a stress compensation voltage corresponding to the applied stress in accordance with a difference between changes in transconductance due to stresses in a first depletion transistor and a first enhancement transistor, and performs compensation for the detection sensitivity in correspondence to the stress applied to the semiconductor sensor.