Stress Control Layer for 3D Semiconductor Warpage Balance

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Solution Overview

Problem

Semiconductor packages face challenges due to high amounts of thermo-mechanical stress resulting from coefficient of thermal expansion (CTE) differences among materials, leading to warping, cracking, and poor bonding efficiency, particularly in thin and high aspect ratio semiconductor substrates.

Innovation Solution

Incorporation of a stress control layer (SC layer) that applies compressive or tensile residual stress to counteract the stress from RDLs, maintaining a planar configuration and improving bonding efficiency by controlling warpage during high-temperature processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If three-dimensional devices are used to improve integration density, then integration density and bandwidth are improved, but warpage and bonding reliability deteriorate due to high thermo-mechanical stress

Engineering Contradiction:

Improveintegration densityVSAvoidbonding reliability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

A stress control layer is introduced as an intermediary component between the semiconductor substrate and the packaging structure. This layer acts as a mediator that compensates for thermo-mechanical stress through its residual stress properties, preventing warpage and improving bonding reliability while maintaining the high integration density of 3D devices.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The stress control layer utilizes changes in residual stress parameters (tensile or compressive stress magnitudes) to counteract the thermo-mechanical stress generated during high-temperature bonding processes. By adjusting the stress state of the layer, the system maintains dimensional stability and prevents warpage without sacrificing integration density.

Inventive Principle:

Principle #35Parameter changes

2Area of stationary object

If thin semiconductor substrates are used to reduce package size, then package area is reduced, but warpage and cracking increase due to high aspect ratio and stress

Engineering Contradiction:

Improvepackage areaVSAvoidresistance to warpage and cracking

Core Design Contradiction:

Area of stationary objectVSStrength

Solution Approach 1:

The stress control layer functions as a counterweight to the thermo-mechanical stress acting on thin semiconductor substrates. By providing opposing residual stress (either tensile or compressive), the layer compensates for the inherent weakness of thin, high aspect ratio substrates, preventing warpage and cracking while maintaining reduced package area.

Inventive Principle:

Principle #8Anti-weight (Counterweight)

3Strength

If high-temperature bonding is performed to achieve reliable connections, then bonding strength is improved, but warpage increases due to thermal expansion differences

Engineering Contradiction:

Improvebonding strengthVSAvoidplanarity

Core Design Contradiction:

StrengthVSShape

Solution Approach 1:

The stress control layer is designed to provide preliminary counter-action to the thermal stress that will be generated during high-temperature bonding. By pre-establishing an opposing residual stress state, the layer prevents warpage from occurring during the bonding process, allowing high bonding strength to be achieved while maintaining planarity.

Inventive Principle:

Principle #9Preliminary anti-action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The SC layer effectively reduces warpage and maintains a planar configuration, enhancing bonding efficiency and reliability of semiconductor devices by balancing residual stresses across different temperature conditions.

Implementation Method 1

the SC layer is configured to apply a compressive stress of at least −100 MPa to the top surface of the first semiconductor layer, or the SC layer is configured to apply a tensile stress of at least 100 MPa to the top surface of the first semiconductor layer

Methodology Applied

Scientific EffectResidual stress:

Implementation Method 2

high amounts of thermo-mechanical stress resulting from coefficient of thermal expansion (CTE) differences among materials

Methodology Applied

Scientific EffectThermo-mechanical stress:

Data Source

PatentUS12512382B2Semiconductor device including stress control layer and methods of forming the same

Publication Date: 2025.12.30 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor device includes a bottom die including a first semiconductor layer, and a first redistribution layer (RDL) disposed on a bottom surface of the first semiconductor layer; a top die disposed on a top surface of the first semiconductor layer and including a second semiconductor layer, and a second RDL disposed on the top surface of the first semiconductor layer; a stress control (SC) layer disposed on the top surface of the first semiconductor layer and side surfaces of the top die; and a dielectric layer disposed on the SC layer, wherein the SC layer is configured to apply a compressive stress of at least −100 MPa to the top surface of the first semiconductor layer, or the SC layer is configured to apply a tensile stress of at least 100 MPa to the top surface of the first semiconductor layer.