Stress-Controlled Hardmask Structure for Sub-100 Nm Pattern Accuracy

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Solution Overview

Problem

Wiggling of patterned features in semiconductor structures is undesired, particularly at sub-100 nm scales, which affects the accuracy and precision of feature/line patterns.

Innovation Solution

A hardmask structure comprising a first ashable hardmask with a stress of about −100 MPa to about 100 MPa, a first dielectric antireflective coating, and a second ashable hardmask is used to form a semiconductor structure, reducing deformation and wiggling issues by controlling internal stress.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional hardmask structures are used for sub-100 nm patterning, then manufacturing capability is maintained, but wiggling of patterned features occurs reducing precision

Engineering Contradiction:

Improvepattern accuracyVSAvoidwiggling deformation

Core Design Contradiction:

Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The patent changes the stress parameter of the bottom ashable hardmask from its conventional range to a specific range of -100 MPa to 100 MPa. This parameter change reduces internal stress-induced deformation and eliminates wiggling of the patterned conductive layer, thereby improving pattern accuracy without compromising manufacturing capability

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent employs a composite hardmask structure consisting of multiple layers with different material properties. The bottom ashable hardmask is specifically engineered with controlled stress characteristics, while the top ashable hardmask provides pattern definition. This composite structure allows the bottom layer to counteract deformation forces that would otherwise cause wiggling, thus improving pattern precision

Inventive Principle:

Principle #40Composite materials

2Ease of manufacture

If hardmask stress is not controlled, then manufacturing process is simpler, but deformation and wiggling issues occur

Engineering Contradiction:

Improveprocess simplicityVSAvoidpattern precision

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent introduces a specific stress parameter range (-100 MPa to 100 MPa) for the bottom ashable hardmask as a controllable variable. By monitoring and adjusting this stress parameter during manufacturing, the process maintains simplicity while ensuring pattern precision is achieved through reduced deformation

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method enhances the accuracy and precision of patterned features, increases contact area, reduces resistance, and improves signal transmission rates in semiconductor structures.

Implementation Method 1

A stress of the first ashable hardmask is from about −100 MPa to about 100 MPa

Methodology Applied

Scientific EffectStress:

Data Source

PatentUS20250232976A1Hardmask structure and method of forming semiconductor structure

Publication Date: 2025.07.17 NAN YA TECH

AI summary

A hardmask structure and a method of forming a semiconductor structure are provided. The hardmask structure includes a first ashable hardmask, a first dielectric antireflective coating, and a second ashable hardmask. The first dielectric antireflective coating is disposed on the first ashable hardmask. The second ashable hardmask is disposed on the first dielectric antireflective coating. A stress of the first ashable hardmask is from about −100 MPa to about 100 MPa.