Stress-Engineered HEMT Assembly Reducing Channel Resistance
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Solution Overview
Problem
High channel resistance and current collapse in nitride semiconductor HEMTs lead to unstable device operation and heat generation, making it difficult to achieve fast switching and reliable performance.
Innovation Solution
A method of manufacturing a transistor assembly by securing an HEMT on a support substrate with applied stress, reducing the warp of the base substrate and maintaining a large lattice constant difference between semiconductor layers, which increases piezo polarization and reduces channel resistance and current collapse.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If an HEMT with high channel resistance is used as a switching element, then the device structure is simpler, but significant heat generation occurs due to thermal loss, making device operation unstable
Solution Approach 1:
The patent applies parameter changes by introducing stress to the base substrate, which modifies the lattice constant of the first semiconductor layer and increases piezo polarization in the second semiconductor layer. This changes the electrical parameters (channel resistance, sheet carrier concentration) to reduce thermal loss while maintaining device stability
2Device complexity
If an HEMT with high channel resistance is used, then the device structure is simpler, but device operation becomes unstable due to heat generation
Solution Approach 1:
The patent changes physical parameters by applying stress to the base substrate, which reduces channel resistance and stabilizes device operation. The stress-induced lattice constant change and increased piezo polarization improve electrical characteristics without complicating the device structure
3Device complexity
If a poor current collapse characteristic is present, then the switching speed is slower, but the device structure is simpler
Solution Approach 1:
The patent improves switching speed by changing the electrical parameters through stress application. The reduced channel resistance and improved current collapse characteristic enable faster switching without increasing device structural complexity
4Ease of manufacture
If the lattice constant of the first semiconductor layer deviates from the theoretical value, then the manufacturing process is simpler, but the piezo polarization is reduced, increasing channel resistance
Solution Approach 1:
The patent applies preliminary anti-action by introducing stress to the base substrate before final device operation. This pre-stress compensates for lattice constant deviations and ensures adequate piezo polarization, achieving both manufacturing simplicity and precision
5Ease of manufacture
If the warp of the base substrate is not reduced, then the manufacturing process is simpler, but the distortion of the first semiconductor layer increases, reducing piezo polarization
Solution Approach 1:
The patent applies preliminary action by reducing the warp of the base substrate through stress application before completing the device assembly. This ensures proper lattice alignment and piezo polarization while maintaining manufacturing feasibility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method significantly reduces channel resistance and improves current collapse characteristics, enhancing the operational stability and efficiency of the HEMT by aligning the lattice constant of the first semiconductor layer with its theoretical value and increasing the tensile stress on the second semiconductor layer.
Implementation Method 1
a tensile stress is applied on the second semiconductor layer... the piezo polarization of the second semiconductor layer increases, thereby increasing the sheet carrier concentration of the 2-dimensional electron gas layer
Implementation Method 2
the base substrate and the support substrate may be bonded together while maintaining the stress... the base substrate has a reduced warp. Therefore, the distortion of the first semiconductor layer is relaxed
Data Source
AI summary
A method for manufacturing a transistor assembly includes the steps of: (a) forming a transistor; (b) polishing a base substrate; and (c) securing the transistor of which the base substrate is polished to a support substrate. The step (a) is a step of forming a first semiconductor layer and a second semiconductor layer on a principle surface of the base substrate. The step (b) is a step of polishing a surface of the base substrate opposite to the principle surface. The step (c) is a step of securing the transistor on the support substrate in the presence of a stress applied on the base substrate in such a direction that a warp of the base substrate is reduced. The base substrate is made of a material different from that of the first semiconductor layer and the second semiconductor layer, and a tensile stress is applied on the second semiconductor layer.