Stress Engineered Multi-Layers for CMOS and Si Nanophotonics Integration
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Solution Overview
Problem
During the fabrication of integrated photonic semiconductor devices, processes beneficial for CMOS devices can be detrimental to photodetectors, leading to crystalline defects, contamination, and chemical attacks, which compromise the integrity and performance of both device types.
Innovation Solution
A multi-layer stack comprising silicon nitride and oxide layers with specific stress properties is used to encapsulate the photonic device, minimizing cracking and contamination by providing a protective barrier during the germanium crystallization process and subsequent wet cleans, while also controlling stress to enhance the operational characteristics of both photonic and CMOS devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard fabrication processes are used for CMOS devices, then CMOS device performance is improved, but photonic device integrity deteriorates due to crystalline defects and contamination
Solution Approach 1:
The patent divides the fabrication process into separate regions: a first region for photonic devices and a second region for CMOS devices. Different fabrication processes are applied to each region independently, allowing standard CMOS processes to be used in the second region while protecting the photonic devices in the first region from harmful effects like contamination and crystalline defects
Solution Approach 2:
The patent introduces an intermediary structure (such as a sacrificial layer or protective coating) between the photonic and CMOS device regions. This intermediary allows the CMOS fabrication processes to proceed normally while preventing direct contamination and harmful interactions with the photonic devices
2Object-affected harmful factors
If encapsulation layers are added to protect photonic devices, then photonic device integrity is improved, but device structure complexity increases
Solution Approach 1:
The patent designs the encapsulation layers to serve multiple functions simultaneously: protecting photonic devices from contamination, providing mechanical stress control, enabling subsequent fabrication steps, and maintaining device performance. This multi-functionality reduces the need for additional separate protective structures, thereby limiting the increase in overall complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The encapsulating multi-layer film stack effectively prevents contamination and chemical attacks, maintains the integrity of both photonic and CMOS devices, and allows for controlled stress application to optimize the performance of the integrated photonic semiconductor structure.
Implementation Method 1
A stress engineered multi-layer film stack for an integrated photonic device is described. The multi-layer film stack may include a first silicon nitride layer having a first stress property, an oxide layer having a stress property, and a second silicon nitride layer having a second stress property
Data Source
AI summary
A method of forming an integrated photonic semiconductor structure having a photonic device and a CMOS device may include depositing a first silicon nitride layer having a first stress property over the photonic device, depositing an oxide layer having a stress property over the deposited first silicon nitride layer, and depositing a second silicon nitride layer having a second stress property over the oxide layer. The deposited first silicon nitride layer, the oxide layer, and the second silicon nitride layer encapsulate the photonic device.