Stress Enhanced MOS Circuits Fabrication via Composite Gate Electrodes
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Solution Overview
Problem
Current integrated circuits (ICs) using MOS transistors lack enhanced mobility of majority carriers, which limits their performance and current-carrying capability, as existing stress engineering methods do not effectively enhance device drive current without increasing device size or capacitance.
Innovation Solution
A stress enhanced MOS circuit is fabricated using a semiconductor substrate with a gate insulator, a gate electrode comprising polycrystalline silicon and a layer of electrically conductive stressed material, and a stress liner to transfer stress to the channel, enhancing mobility through a replacement gate method that maintains stress during back-end processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional stress engineering methods are used, then device drive current is increased, but device size or device capacitance must be increased
Solution Approach 1:
The patent changes the physical and chemical parameters of the gate electrode by using a composite structure with polycrystalline silicon and stressed material layers, and by controlling the stress state during fabrication processes, to achieve high drive current without increasing device size
Solution Approach 2:
The gate electrode is formed as a composite structure combining polycrystalline silicon and stressed material layers, where each material contributes different properties - the polycrystalline silicon provides structural integrity while the stressed material layer provides the stress necessary for high carrier mobility and drive current
2Productivity
If conventional stress engineering methods are used, then device drive current is increased, but device capacitance must be increased
Solution Approach 1:
The patent changes the capacitance parameter by optimizing the gate electrode structure and stress distribution, achieving high drive current through stress-induced mobility enhancement rather than through increased capacitance
3Reliability
If replacement gate method is used to maintain stress during back-end processing, then stress transfer to channel is improved, but fabrication process complexity increases
Solution Approach 1:
The replacement gate method performs preliminary stress engineering actions during front-end processing where the gate structure is formed, allowing stress to be maintained and transferred effectively through subsequent back-end processing steps without requiring additional stress application steps
Solution Approach 2:
The gate electrode structure acts as an intermediary that transfers stress from the fabrication process to the channel, maintaining stress integrity through the replacement gate method and ensuring effective stress transfer to enhance carrier mobility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly enhances majority carrier mobility, achieving up to 2.6 times the mobility of conventional devices, while maintaining thermal stability and effectively transferring stress to the channel, thereby improving circuit performance without increasing device size or capacitance.
Implementation Method 1
A stress liner overlies the side walls of the gate electrode
Implementation Method 2
The mobility of holes, the majority carrier in a P-channel MOS (PMOS) transistor, and the mobility of electrons, the majority carrier in an N-channel MOS (NMOS) transistor, can be enhanced by applying an appropriate stress to the channel
Data Source
AI summary
A stress enhanced MOS circuit and methods for its fabrication are provided. The stress enhanced MOS circuit comprises a semiconductor substrate and a gate insulator overlying the semiconductor substrate. A gate electrode overlies the gate insulator; the gate electrode has side walls and comprising a layer of polycrystalline silicon having a first thickness in contact with the gate insulator and a layer of electrically conductive stressed material having a second thickness greater than the first thickness overlying the layer of polycrystalline silicon. A stress liner overlies the side walls of the gate electrode.