Stress Enhanced Semiconductor Device Corner Rounding Control

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Solution Overview

Problem

The challenge in semiconductor device fabrication is the variability in active width caused by corner rounding, which affects the drive current capability and predictability of MOS transistor performance, especially as critical dimensions shrink, leading to increased complexity and reduced performance gains from scaling.

Innovation Solution

The implementation of stress enhanced semiconductor devices involves a substrate with an active region and two types of stress layers, where a first-type stress layer is applied over the active region and a second-type stress layer is placed adjacent to it, reducing stress enhancement and minimizing corner rounding effects without compromising drive current capability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If stress layers are applied to enhance drive current, then device performance improves, but corner rounding variability increases

Engineering Contradiction:
Improvedrive current capabilityVSAvoidactive width uniformity
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The stress layer is segmented into different regions: a first stress layer overlying the active region and a second stress layer in the inactive region. This segmentation allows different stress characteristics in different areas, maintaining drive current enhancement while reducing corner rounding effects at the boundaries.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different stress layers are applied to different regions of the device. The first stress layer provides stress enhancement in the active region for improved drive current, while the second stress layer in the inactive region provides a stress gradient that reduces corner rounding variability, creating local quality optimization.

Inventive Principle:
Principle #3Local quality

2Productivity

If device size is reduced to increase integration density, then more devices fit in IC, but performance gain from scaling becomes limited

Engineering Contradiction:
Improveintegration densityVSAvoiddevice performance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The invention changes the stress parameter in the semiconductor device by introducing specific stress layers with controlled stress magnitudes and directions. This allows performance enhancement through stress-induced mobility improvement rather than relying solely on dimensional scaling, enabling continued performance gains as devices shrink.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If active region width is increased to improve drive current, then current capability increases, but corner rounding effects become more significant

Engineering Contradiction:
Improvedrive current capabilityVSAvoidcorner rounding variability
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The second stress layer acts as a counterweight to the corner rounding effects by providing a compensating stress gradient in the inactive region. This counter-stress reduces the variability caused by corner rounding while the first stress layer maintains the drive current enhancement, effectively canceling out the harmful effects.

Inventive Principle:
Principle #8Anti-weight (Counterweight)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for more uniform active widths, reducing corner rounding and maintaining drive current capability without increasing the overall layout area or gate lengths, thereby enhancing the reliability and performance of MOS transistors.

Implementation Method 1

By applying an appropriate uniaxial stress to the channel of the MOS transistor, the mobility of the majority carrier in the channel can be increased which increases drive current thereby improving performance of the MOS transistor

Methodology Applied
Scientific EffectStress-induced mobility enhancement: Piezoresistive Effect

Data Source

PatentUS7638837B2Stress enhanced semiconductor device and methods for fabricating same
Publication Date: 2009.12.29 GLOBALFOUNDRIES US INC
  • US7638837B2 patent drawing
  • US7638837B2 patent drawing
  • US7638837B2 patent drawing

AI summary

A stress-enhanced semiconductor device is provided which includes a substrate having an inactive region and an active region, a first-type stress layer overlying at least a portion of the active region, and a second-type stress layer. The active region includes a first lateral edge which defines a first width of the active region, and a second lateral edge which defines a second width of the active region. The second-type stress layer is disposed adjacent the second lateral edge of the active region.