Stress-Inducing Gate Cut Plugs for Sub-10nm GAA Scaling
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Solution Overview
Problem
The challenge of maintaining mobility improvement and short channel control in multi-gate transistors as device dimensions scale below the 10 nanometer node, particularly in bulk silicon substrates, is exacerbated by constraints on lithographic processes and trade-offs between feature dimension and spacing, leading to issues in gate cut plug fabrication and performance optimization.
Innovation Solution
The implementation of stress-inducing gate cut plugs, formed after metal gate processing, which include deep via bars and selective modulation of channel stress, allowing for a 'plug-last' approach that ensures a clean interface and seamless work function metal deposition, reducing space constraints and improving metal fill capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device dimensions are scaled down below 10 nanometer node, then increased density of functional units is achieved, but maintaining mobility improvement and short channel control becomes challenging
Solution Approach 1:
The patent transitions from planar gate structures to three-dimensional gate-all-around structures that completely surround the channel in multiple dimensions. This dimensional change provides superior electrostatic control over the channel, enabling effective short channel control at sub-10nm nodes while maintaining high device density.
Solution Approach 2:
The patent employs composite material structures including semiconductor-sacrificial semiconductor heterostructures for nanowire formation, and combines multiple dielectric materials (first dielectric material and second dielectric material with different stress properties) in the gate cut plug to achieve both structural integrity and stress-induced mobility improvement.
2Productivity
If feature dimension is reduced, then increased device density is achieved, but spacing between features and lithographic process constraints worsen
Solution Approach 1:
The gate cut plug is segmented into multiple functional regions: a first portion extending from the gate electrode to a first depth, a second portion extending to a second depth, and a third portion filling the remaining space. This segmentation allows each portion to be optimized for specific functions (electrical connection, stress induction, structural support) and simplifies the fabrication process by enabling sequential formation steps that are more compatible with lithographic constraints.
Solution Approach 2:
The patent performs preliminary actions by forming the gate-all-around structure and gate electrode before forming the gate cut plug. This sequence ensures that the plug is precisely aligned with previously formed structures and that interface cleanliness is maintained, reducing the need for additional alignment steps that would exacerbate lithographic constraints.
3Ease of manufacture
If conventional gate cut plug fabrication is used, then process simplicity is maintained, but interface cleanliness and metal fill capability deteriorate
Solution Approach 1:
The gate cut plug is formed after metal gate processing is complete, ensuring a clean interface between the plug and the gate electrode. This preliminary formation of the plug structure before subsequent metal deposition eliminates contamination risks and ensures seamless interfaces, improving metal fill capability without significantly complicating the overall process.
Solution Approach 2:
Different portions of the gate cut plug are formed with different materials and properties optimized for their specific locations and functions. The first portion uses a first dielectric material optimized for electrical isolation, the second portion uses a second dielectric material optimized for stress induction, and the third portion provides structural support. This local optimization ensures each region contributes to overall interface cleanliness and metal fill capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances strain optimization and reduces power network resistance, enabling reduced cell height and improved performance by delivering power from the wafer backside, while maintaining robust power delivery and minimizing voltage drop.
Implementation Method 1
selective modulation of channel stress, allowing for a 'plug-last' approach that ensures a clean interface and seamless work function metal deposition
Data Source
AI summary
Integrated circuit structures having stress-inducing gate cut plugs are described. For example, a structure includes a first vertical stack of horizontal nanowires or fin over a first sub-fin. A first gate structure is over the first vertical stack of horizontal nanowires or fin. A second vertical stack of horizontal nanowires or fin is over a second sub-fin. A second gate structure is over the second fin. A gate cut separates a first gate electrode of the first gate structure from a second gate electrode of the second gate structure. A gate cut fill structure is in the gate cut, the gate cut fill structure including a first dielectric material portion in contact with the first gate electrode, a conductive via portion, and a second dielectric material portion in contact with the second gate electrode. The conductive via portion separates the first dielectric material portion from the second dielectric material portion.