Stress-Generating Buried Insulator Plug for SOI Devices
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current stress-generating structures for semiconductor-on-insulator (SOI) devices are ineffective due to the thin top semiconductor layer, which limits stress transfer, and are not compatible with existing semiconductor processing after trench isolation formation.
Innovation Solution
A stress-generating structure is created by forming a stack of pad layers on an SOI substrate, including a deep trench with a stress-generating silicon nitride plug and a silicon oxide plug, which applies compressive or tensile stress to the top semiconductor region, and is compatible with existing processing sequences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shallow trench isolation liners are used to generate stress in bulk substrates, then stress can be applied to improve carrier mobility, but the method is ineffective for semiconductor-on-insulator devices because the thin top semiconductor layer (5-30 nm) limits stress transfer compared to bulk substrates where trench depth is 300-450 nm
Solution Approach 1:
The patent transitions from shallow trench isolation (2D surface-level stress generation) to deep trench isolation extending below the buried insulator layer (3D volumetric stress generation). This dimensional change allows the stress-generating structure to penetrate through the thin top semiconductor layer and apply effective stress to the channel region in SOI devices, resolving the incompatibility between bulk substrate stress methods and thin-film SOI structures.
Solution Approach 2:
The stress-generating trench structure is formed before device fabrication, establishing the stress field in advance. The deep trench is etched through the top semiconductor layer and buried insulator layer, and filled with stress-generating material (silicon nitride or silicon oxide) to create predetermined compressive or tensile stress regions that will enhance carrier mobility throughout subsequent processing steps.
2Reliability
If deep trench isolation is used to generate stress in SOI devices, then effective stress can be transferred to the thin top semiconductor layer, but the processing sequence must be modified which complicates manufacturing
Solution Approach 1:
The trench isolation structure is segmented into distinct functional regions: the deep trench extending below the buried insulator layer for stress generation, the stress-generating material fill (silicon nitride or silicon oxide), and the isolation function. This segmentation allows each component to be optimized independently while integrating into the existing SOI device fabrication process.
Solution Approach 2:
The patent modifies the trench depth parameter from shallow (300-450 nm in bulk substrates) to deep (extending below the buried insulator layer in SOI devices), and changes the fill material parameters to include stress-generating materials like silicon nitride or silicon oxide. These parameter changes enable effective stress transfer to the thin top semiconductor layer while maintaining compatibility with standard semiconductor processing techniques.
3Ease of manufacture
If silicon oxide is used as trench fill material in existing processing sequences, then manufacturing is simplified, but no stress is generated to improve device performance
Solution Approach 1:
The patent employs composite material strategies by selecting fill materials that combine stress-generating properties with process compatibility. Silicon nitride provides tensile stress and is compatible with standard deposition processes, while silicon oxide provides compressive stress and matches existing isolation material processes. These composite material choices enable simultaneous achievement of stress generation and manufacturing simplicity.
Solution Approach 2:
The stress-generating fill material acts as an intermediary between the deep trench structure and the top semiconductor layer, transferring mechanical stress to the channel region. Materials like silicon nitride and silicon oxide serve as mediators that can be deposited using existing process equipment while providing the necessary stress field to enhance carrier mobility in the thin top semiconductor layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The structure effectively generates stress in the semiconductor region, enhancing carrier mobility and transistor performance, while being compatible with conventional semiconductor processing steps.
Implementation Method 1
When stress is applied to the channel within an active area of a semiconductor transistor, the mobility of carriers, and as a consequence, the transconductance and the on-current of the transistor are altered
Implementation Method 2
the applied stress and the resulting strain on the semiconductor structure within the channel affects the band gap structure (i.e., breaks the degeneracy of the band structure) and changes the effective mass of carriers
Implementation Method 3
A stress-generating nitride material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried nitride plug
Data Source
AI summary
A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.