Stress Inducing Layer for Magnetic Memory Write Control
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Solution Overview
Problem
Magnetic memory circuits, such as MRAM, face challenges in efficiently manipulating the magnetic field required to write bits into magnetic tunnel junction (MTJ) stacks, limiting the flexibility and efficiency of the write process.
Innovation Solution
Incorporating a stress inducing layer, such as titanium nitride, adjacent to the free layer in the MTJ stack to provide tensile or compressive stress, which manipulates the magnetic field and write voltage, allowing for different stress magnitudes and types by varying thickness, material, deposition conditions, and the presence of a dummy layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a stress inducing layer is added adjacent to the free layer, then the flexibility and efficiency of writing operations is improved by tuning write voltages, but the device complexity increases due to additional layers and processing steps
Solution Approach 1:
The patent applies parameter changes by introducing a stress inducing layer that modifies the magnetic anisotropy of the free layer through mechanical stress. This allows tuning of the write field magnitude and polarity by changing the stress state (tensile or compressive) of the free layer, thereby adjusting write voltages to optimize writing operations without fundamentally changing the core MTJ structure
Solution Approach 2:
The patent uses composite materials by combining the stress inducing layer (made of materials like titanium nitride or tungsten) with the existing MTJ stack layers. This composite structure enables the stress inducing layer to apply controlled mechanical stress to the free layer, modifying its magnetic properties and enabling flexible write voltage tuning while maintaining compatibility with standard CMOS processing
2Adaptability or versatility
If multiple MTJ stacks use different stress inducing layers to operate with different write voltages, then the adaptability of the memory circuit is improved, but the manufacturing precision requirements increase due to varying deposition conditions and layer configurations
Solution Approach 1:
The patent applies local quality by allowing different regions (MTJ stacks) to have different stress inducing layer configurations tailored to their specific operational requirements. Each MTJ stack can be customized with specific stress inducing layer materials, thicknesses, and stress states to achieve desired write voltages, while the overall manufacturing process remains standardized and compatible with existing CMOS fabrication lines
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the flexibility and design of magnetic memory circuits by allowing for precise tuning of write voltages and different operational states, improving the write process efficiency and flexibility.
Implementation Method 1
A stress inducing layer is disposed adjacent to the free layer, to provide tensile or compressive stress to the free layer in order to manipulate a magnetic field that is required to write a bit into the MTJ stack
Data Source
AI summary
Memory circuit comprising an addressable magnetic tunnel junction (MTJ) stack, forming a magnetic storage element in the circuit. The MTJ stack comprises a tunnel oxide layer between a free layer and a fixed layer. A stress inducing layer is disposed adjacent to the free layer to provide tensile or compressive stress to the free layer, in order to manipulate a magnetic field that is required to write a bit into the MTJ stack. Method of using the memory circuit is also proposed.