Stress-Layer GaN HEMT Structure for Higher Mobility and Lower On-Resistance
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Solution Overview
Problem
Current GaN-based high electron mobility transistors (HEMTs) face limitations in optimizing carrier mobility and on-resistance, which affects their performance in high-frequency applications.
Innovation Solution
The method involves forming a p-type semiconductor layer with adjacent compressive and tensile stress layers to enhance carrier mobility, specifically by forming a buffer layer, barrier layer, and stress layers using epitaxial growth processes like MBE or MOCVD, and patterning these layers to create stress regions that increase carrier mobility and reduce on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional GaN-based HEMT fabrication is used, then basic transistor functionality is achieved, but carrier mobility is limited and on-resistance is high
Solution Approach 1:
The patent applies local quality by introducing stress layers with specific mechanical properties at particular locations within the HEMT structure. The first and second stress layers are positioned adjacent to the channel region, creating localized stress fields that modify carrier mobility specifically in the active channel area without affecting other regions of the device. This localized approach optimizes carrier transport where it matters most while maintaining overall device functionality.
Solution Approach 2:
The patent utilizes parameter changes by modifying the mechanical stress state of the channel region through the introduction of stress layers with different lattice constants. By changing the stress parameters (tensile or compressive) in the channel area, the carrier mobility is enhanced through piezoresistive effects. The stress layers alter the band structure and effective mass of carriers, fundamentally changing the electrical transport parameters in the channel.
2Reliability
If stress layers are added to enhance carrier mobility, then device performance improves, but fabrication process complexity increases
Solution Approach 1:
The patent merges the stress layer formation with the existing epitaxial growth process. The stress layers are grown in-situ using MBE or MOCVD techniques alongside the barrier layer and channel layer formation. This integration means that the stress layers are deposited as part of the continuous epitaxial sequence without requiring separate fabrication steps, tooling changes, or additional processing equipment. The merging of processes adds functional complexity but maintains procedural simplicity.
Solution Approach 2:
The stress layers serve multiple functions simultaneously: they provide mechanical stress to enhance carrier mobility, act as part of the epitaxial structure, and can be integrated with existing device fabrication flows. The same epitaxial growth equipment and techniques used for creating the GaN layers are also used for forming the stress layers, making the process universally applicable to existing HEMT manufacturing lines without requiring specialized equipment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases carrier mobility by approximately 66% and lowers on-resistance by a factor of 2.7, while enhancing the cut-off frequency (fT) of the HEMT.
Implementation Method 1
forming a buffer layer on a substrate, forming a barrier layer on the buffer layer... using epitaxial growth processes like MBE or MOCVD
Implementation Method 2
forming a compressive stress layer adjacent to one side of the p-type semiconductor layer, and then forming a tensile stress layer adjacent to another side of the p-type semiconductor layer... to enhance carrier mobility
Data Source
AI summary
A method for fabricating a high electron mobility transistor (HEMT) includes the steps of first forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a compressive stress layer adjacent to one side of the p-type semiconductor layer, and then forming a tensile stress layer adjacent to another side of the p-type semiconductor layer.