Stress Creating Layer Formation Without Blocking Layer
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Solution Overview
Problem
The existing methods for manufacturing semiconductor devices with stress creating layers in CMOS transistors face issues such as residue formation and etching differences, which deteriorate device characteristics and leakage characteristics, particularly due to the need for a blocking layer and subsequent photolithography processes.
Innovation Solution
A method involving the formation of first and second gates, conductive impurity regions, spacers, and semiconductor layers on a semiconductor substrate, followed by selective epitaxial growth of SiGe layers in recess areas to create stress creating layers, with specific etching and impurity region formation steps to achieve compressive and tensile stress in PMOS and NMOS transistors respectively, without the need for a blocking layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a blocking layer is formed to create stress creating layer in PMOS transistor recessed source and drain areas, then the stress creating layer can be formed selectively, but residues exist in the blocking layer and device characteristics deteriorate
Solution Approach 1:
The patent removes the blocking layer from the process entirely. Instead of forming a blocking layer to mask the NMOS transistor during stress creating layer formation, the method uses direct selective epitaxial growth on the PMOS recessed source and drain areas without any masking layer, thereby eliminating residue formation and associated reliability issues
Solution Approach 2:
The patent introduces a spacer layer as an intermediary structure that enables selective stress creating layer formation. The spacer, formed on the sidewalls of the gate, serves as a physical barrier that prevents epitaxial growth on the NMOS areas without requiring a separate blocking layer, thus achieving selective formation without residues
2Manufacturing precision
If photolithography process is used to form blocking layer, then selective stress creating layer can be formed, but manufacturing process complexity increases
Solution Approach 1:
The patent eliminates the photolithography process step entirely by removing the blocking layer requirement. The selective formation of stress creating layers is achieved through direct selective epitaxial growth guided by the spacer structure, bypassing the need for photoresist coating, patterning, and removal steps
Solution Approach 2:
The spacer structure serves a dual function: it acts as both a structural element defining the active region and as a self-aligned mask for selective epitaxial growth. This self-service approach eliminates the need for separate photolithography masking steps, simplifying the manufacturing process
3Ease of repair
If blocking layer is removed after forming stress creating layer, then the blocking layer can be discarded, but residues remain and device characteristics deteriorate
Solution Approach 1:
The patent removes the blocking layer from the process entirely, eliminating the need for its subsequent removal. By using direct selective epitaxial growth without a blocking layer, the method prevents residue formation at the source, thereby maintaining device characteristics without requiring any blocking layer removal steps
Solution Approach 2:
The spacer layer serves as an intermediary that enables selective stress creating layer formation without requiring a blocking layer. This intermediary structure achieves the same selective formation goal without the harmful side effect of residue formation that occurs when blocking layers are removed
4Ease of manufacture
If etching process is used to form contact holes, then the insulation layer can be removed, but etching differences occur and leakage characteristics deteriorate
Solution Approach 1:
The patent applies local quality by forming stress creating layers with different properties in different regions. The PMOS transistor receives a compressive stress creating layer while the NMOS transistor receives a tensile stress creating layer, with each layer optimized for its specific transistor type, thereby preventing etching differences and leakage issues
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process by eliminating the need for a blocking layer and reduces residue and etching-related issues, thereby improving device characteristics and leakage performance in CMOS transistors.
Implementation Method 1
selective epitaxial growth of SiGe layers in recess areas to create stress creating layers
Data Source
AI summary
Provided is a simplified method of manufacturing a semiconductor device having a stress creating layer. A first conductive first impurity region is formed on a semiconductor substrate on both sides of a first gate of a first area of the semiconductor substrate, and a second conductive second impurity region is formed on the semiconductor substrate on both sides of a second gate of a second area. First and second spacers are formed on sidewalls of the first and second gates, respectively. First and second semiconductor layers are formed in portions of the semiconductor substrate so as to contact the first and second impurity regions, respectively. The second semiconductor layer is removed. First and second barrier layers are formed in the first and second contact holes of the insulation layer, respectively.