Stress Propagating Layer for Narrow Semiconductor Sawing Lanes
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Solution Overview
Problem
The challenge of efficiently separating semiconductor chips with narrower sawing lanes due to increased stress and crack propagation during wafer sawing, leading to reduced yield and structural integrity issues.
Innovation Solution
Incorporating a stress propagating layer with a second dielectric layer and stress propagating patterns arranged at intervals to disperse sawing stress, preventing lateral diffusion and ensuring complete chip separation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the sawing lane is narrowed to increase chip integration, then chip integration is improved, but chip separation becomes more difficult due to increased stress and crack propagation
Solution Approach 1:
The patent introduces a stress propagating layer with periodically arranged stress propagating patterns (such as through-holes or voids) that segment the stress distribution during sawing. These patterns are arranged at specific intervals to control stress propagation, allowing the stress to be distributed across multiple discrete locations rather than concentrating continuously, thereby enabling complete chip separation even in narrow sawing lanes
Solution Approach 2:
The stress propagating layer acts as an intermediary between the device layer and the sawing process. It mediates the stress generated during sawing by providing a controlled path for stress propagation through its periodic patterns, preventing stress from directly affecting the device structures while facilitating complete chip separation
2Length of moving object
If the sawing lane width is reduced, then chip dimension is improved, but stress concentration increases leading to crack propagation
Solution Approach 1:
The stress propagating layer introduces local variations in material properties through periodically arranged patterns (such as through-holes or voids). These local modifications create specific zones where stress can propagate controllably, while other zones maintain structural integrity. The patterns are strategically positioned to localize stress propagation away from critical device structures
Solution Approach 2:
By segmenting the stress propagating layer into periodic patterns, the patent creates discrete stress propagation paths. This segmentation prevents continuous stress concentration across the entire sawing lane, instead distributing stress across multiple localized regions, thereby reducing overall stress concentration on individual chip structures
Data Source
AI summary
A semiconductor structure includes a base layer, a device layer, and a stress propagating layer. The device layer is located on the base layer. The device layer includes a first dielectric layer and device structures. The first dielectric layer fills the device layer and isolates the device structures. The stress propagating layer is located on the device layer, includes a second dielectric layer and a plurality of stress propagating patterns arranged at intervals. The second dielectric layer fills the stress propagating layer and isolates the stress propagating patterns.