Stress Liner Structure for PFET Hole Mobility in Nanosheet Channels
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Solution Overview
Problem
The semiconductor industry faces challenges in enhancing hole mobility in p-type FETs (PFETs) due to the complexity of scaling down semiconductor devices, which affects device performance and efficiency.
Innovation Solution
The implementation of stress liners, specifically made of silicon oxide or silicon germanium oxide, is used to exert longitudinal compressive stress on nanostructured channel regions between source/drain regions, improving hole mobility by increasing the pressure on gate structures and transferring it as compressive stress within the channel regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device dimensions are scaled down to increase storage capacity and processing speed, then storage capacity and processing speed are improved, but manufacturing complexity increases
Solution Approach 1:
The patent changes the physical and chemical parameters of the channel region by introducing stress liners made of specific materials (silicon oxide, silicon germanium oxide) with controlled thicknesses and compositions. This modifies the stress state and crystal structure of the channel, thereby changing carrier mobility parameters to improve processing speed without requiring further dimension scaling
Solution Approach 2:
The stress liner is applied locally and selectively to specific channel regions rather than uniformly across the entire device. This localized modification allows targeted improvement of hole mobility in PFETs while maintaining other device characteristics, thus improving productivity without proportionally increasing overall manufacturing complexity
2Reliability
If stress liners are used to enhance hole mobility in PFETs, then hole mobility is improved, but device structure complexity increases
Solution Approach 1:
The stress liner acts as an intermediary layer between the gate structure and the channel region. It mediates the stress transfer from the gate to the channel, enabling mobility enhancement without directly modifying the gate or channel structures. This intermediary approach improves hole mobility while adding only a thin functional layer rather than complex structural modifications
Solution Approach 2:
The stress liner utilizes composite material systems including silicon oxide and silicon germanium oxide with varying germanium concentrations. These composite materials provide tailored mechanical and electrical properties to achieve optimal stress induction and hole mobility enhancement, improving reliability through material composition optimization rather than structural complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances hole mobility in PFETs, leading to improved device performance by increasing the efficiency of hole flow in channel regions, thereby addressing the limitations of current semiconductor manufacturing processes.
Implementation Method 1
The stress liner is disposed over the etch stop layer and configured to provide compressive stress in the nanostructured channel region
Data Source
AI summary
A semiconductor device and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a nanostructured channel region disposed on the substrate, a gate structure surrounding the nanostructured channel region, a source/drain (S/D) region disposed adjacent to the nanostructured channel region, an etch stop layer (ESL) disposed on the S/D region, a stress liner disposed on the etch stop layer and configured to provide compressive stress in the nanostructured channel region, an inter-layer dielectric (ILD) layer disposed on the stress liner, and a contact structure disposed in the S/D region, ESL, stress liner, and ILD layer.