Stress Memorization Layer Mitigates Wafer Bowing in 3D NAND
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Solution Overview
Problem
In semiconductor device manufacturing, increased stresses in substrates due to stacked layers, such as in 3-D NANDs, lead to wafer directional bowing, complicating lithography alignment and reducing device quality and increasing costs.
Innovation Solution
A stress memorization layer is formed by implanting the substrate's second main side to create an amorphous implant area, depositing a stress liner, annealing to form a stress memorization layer, and then removing the stress liner, which helps mitigate substrate stress and wafer bowing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple layers are stacked to form 3-D NAND structures, then device capacity and integration density are improved, but substrate stress increases causing wafer bowing
Solution Approach 1:
The patent applies preliminary anti-action by forming a stress memorization layer on the backside of the substrate before the stacking process. This layer is designed to generate compensatory stress that counteracts the stress that will be generated by the stacked layers, thereby preventing wafer bowing before it occurs during device fabrication.
Solution Approach 2:
The patent implements local quality by creating a stress memorization layer with specific mechanical properties on the backside of the substrate in a localized region. This allows differential stress compensation across the substrate, enabling precise control over wafer flatness while maintaining high device capacity through multi-layer stacking.
2Productivity
If substrate stress increases due to stacked layers, then device integration is improved, but lithography alignment becomes challenging
Solution Approach 1:
The stress memorization layer is formed in advance to preemptively counteract stress-induced substrate deformation. By establishing this compensatory stress mechanism before lithography processes, the substrate maintains proper flatness and dimensional stability, ensuring accurate lithography alignment throughout the device fabrication sequence.
Solution Approach 2:
The patent performs preliminary action by preparing the stress memorization layer and characterizing substrate stress behavior before proceeding to lithography and stacking operations. This advance preparation enables optimization of the stress compensation mechanism to ensure subsequent lithography alignment precision while achieving high device integration.
3Productivity
If wafer bowing occurs due to substrate stress, then device manufacturing continues, but device quality decreases
Solution Approach 1:
The stress memorization layer is configured to generate compensatory stress that counteracts the stress from stacked layers, preventing wafer bowing that would otherwise degrade device quality. This preliminary anti-action mechanism maintains substrate flatness and mechanical stability throughout manufacturing, ensuring high device reliability while enabling continuous production.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces wafer bowing, enhances device reliability, and creates a long-lasting stress memorization layer that compensates for directional stresses, improving the quality and cost-effectiveness of semiconductor devices.
Implementation Method 1
implanting the second main side of the substrate to form an amorphous implant area
Implementation Method 2
annealing the stress liner to form a stress memorization layer in the amorphous implant area
Data Source
AI summary
Embodiments herein are directed to methods and devices having a stress memorization layer along a side of a substrate. In some embodiments, a method may include providing a substrate having a first main side opposite a second main side, implanting the second main side of the substrate to form an amorphous implant area, forming a stress liner over the second main side of the substrate, and annealing the stress liner to form a stress memorization layer in the amorphous implant area.