Stress Memorization Technique Wafer Flatness Control
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Solution Overview
Problem
The existing stress memorization technique for semiconductor devices results in non-uniform wafer flatness due to aggressive batch wet etching, leading to photolithographic defocus defects and low yield, especially at advanced technology nodes like 28 nm and below.
Innovation Solution
A method involving single-wafer wet etching followed by batch wet etching to remove the second silicon nitride layer, while preserving part of the first silicon nitride layer on the back surface, which protects the polysilicon gate during cleaning and maintains wafer flatness during the back-end-of-line photolithography process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If one-step batch wet etching is used to remove silicon nitride film, then the silicon nitride film is completely removed from the wafer front surface, but the polysilicon film on the back surface becomes exposed and wafer flatness deteriorates
Solution Approach 1:
The patent divides the silicon nitride film removal process into two separate steps: first removing the silicon nitride film from the front surface, then removing it from the back surface. This segmentation allows control over the etching process to prevent exposure of the polysilicon film on the back surface while maintaining wafer flatness.
Solution Approach 2:
The patent performs preliminary action by removing the silicon nitride film from the front surface first, then proceeds to remove it from the back surface in a controlled manner. This preliminary removal from the front surface allows subsequent processes to be performed without the harmful effects of having the back surface polysilicon exposed.
2Reliability
If the back surface is cleaned with high etching speed solution to remove metal ions, then metal ion concentration is reduced to safe range, but the polysilicon gate is unevenly etched causing photolithographic defocus defects
Solution Approach 1:
The patent performs preliminary action by preserving the polysilicon gate structure on the back surface through controlled etching. This preliminary protection ensures that subsequent cleaning processes can be performed without causing uneven etching of the polysilicon gate, thereby preventing photolithographic defocus defects.
Solution Approach 2:
The patent applies beforehand cushioning by maintaining a protective layer or controlled etching condition that cushions the polysilicon gate from aggressive etching during the cleaning process. This prior cushioning prevents the high etching speed solution from causing non-uniform removal of the polysilicon gate structure.
3Ease of operation
If mechanical stages contact the wafer back surface frequently, then wafer handling is enabled, but contamination occurs at contact points causing localized etching speed variations
Solution Approach 1:
The patent extracts or removes the contaminated areas from affecting the etching process by using a two-step etching approach. The first step addresses the bulk removal, and the second step can be optimized to account for localized contamination, effectively taking out the harmful effect of contaminated contact points.
Solution Approach 2:
The patent applies local quality by recognizing that different areas of the back surface have different conditions due to mechanical contact contamination. The etching process is adjusted to account for these local variations, applying different etching conditions to different regions to achieve uniform overall results.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves wafer flatness and eliminates photolithographic defocus defects, enhancing product yield by preventing uneven etching and maintaining surface uniformity during the back-end-of-line photolithography process.
Implementation Method 1
the first silicon nitride layer remaining on the back surface of the semiconductor substrate protects the polysilicon layer on the back surface of the semiconductor substrate from being etched during cleaning
Implementation Method 2
performing first-time wet etching and then performing second-time wet etching
Data Source
AI summary
The application discloses a method of applying the stress memorization technique in making the semiconductor device which includes: step 1: forming a front gate structure on a silicon wafer having front and back surfaces; step 2: forming sidewalls including a first silicon nitride sidewall, a first silicon nitride layer corresponding to the first silicon nitride sidewall covering a first polysilicon layer on the wafer's back surface; step 3: growing a second silicon nitride layer on the wafer's front surface; step 4: etching the silicon nitride after stress transfer is completed, including: step 41: performing front single-wafer wet etching; step 42: performing batch wet etching to completely remove the second silicon nitride layer and reduces the thickness of the first silicon nitride layer on the back surface; step 5: completing the subsequent process. The application can improve the wafer flatness for improved photolithography for back-end-of-line processes and thereby increasing product yield.