Stress Mitigation Resin for Semiconductor Lead Frame
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Solution Overview
Problem
Semiconductor devices face insulation reliability issues due to peeling and cracking of sealing resins caused by thermal cycles, particularly at the interface between low linear expansion coefficient members and lead frames, leading to voids and reduced insulation characteristics.
Innovation Solution
A stress mitigation resin with a lower elastic modulus than the sealing resin is applied to the ends of the lead frame to mitigate stress and prevent peeling and cracking, while ensuring proper resin flow and reducing voids.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a sealing resin with heavily added ceramic filler is used to reduce linear expansion coefficient, then the linear expansion coefficient is reduced, but the elastic modulus increases and toughness decreases
Solution Approach 1:
The patent applies a stress mitigation resin with different properties (lower elastic modulus, higher toughness) specifically at the lead frame end where stress concentrates, rather than uniformly changing the entire sealing resin. This local modification addresses the toughness deficiency only where needed while maintaining the low linear expansion coefficient of the main sealing resin body.
Solution Approach 2:
The patent creates a composite structure by combining the main sealing resin (with ceramic filler for low linear expansion) and a stress mitigation resin (with lower elastic modulus for stress absorption) at the lead frame interface. This composite approach allows each material to perform its specialized function.
2Reliability
If a stress mitigation resin is applied to the entire region including narrow gap areas, then peeling and cracking are suppressed, but voids are left due to resin flow restriction
Solution Approach 1:
The patent precisely controls the application location of the stress mitigation resin to the lead frame end region, avoiding narrow gap areas where resin flow is critical. This localized application ensures stress mitigation without interfering with the sealing resin's ability to flow and fill gaps, preventing void formation.
Solution Approach 2:
The patent applies the stress mitigation resin only partially to the lead frame end region rather than the entire surface, which is sufficient to address the stress concentration issue while leaving narrow gap areas accessible for proper resin flow and void-free filling.
3Reliability
If the elastic modulus of the sealing resin is increased to suppress peeling, then peeling resistance is improved, but the resin becomes more prone to cracking under thermal stress
Solution Approach 1:
The patent creates a gradient structure where the main sealing resin body has high elastic modulus for peeling resistance, while the stress mitigation resin layer at the lead frame end has lower elastic modulus to absorb thermal stress and prevent cracking. This local differentiation resolves the contradiction between peeling resistance and cracking resistance.
Solution Approach 2:
The stress mitigation resin layer is applied beforehand at the lead frame end to act as a cushion that absorbs thermal stress before it can propagate into the main sealing resin body, preventing cracking while the main resin maintains its high modulus for peeling resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses peeling and cracking of the sealing resin, enhances insulation reliability, and prevents voids, even under high-temperature conditions, thereby improving the overall performance of semiconductor and power conversion devices.
Implementation Method 1
a stress mitigation resin partially applied to an end of the lead frame and having a lower elastic modulus than that of the sealing resin
Implementation Method 2
a sealing resin covering the semiconductor chip, the insulation substrate, and the lead frame
Implementation Method 3
a lead frame bonded to an upper surface of the semiconductor chip
Data Source
AI summary
A semiconductor chip (6) is disposed on the insulation substrate (2). A lead frame (8) is bonded to an upper surface of the semiconductor chip (6). A sealing resin (12) covers the semiconductor chip (6), the insulation substrate (2), and the lead frame (8). A stress mitigation resin (13) having a lower elastic modulus than that of the sealing resin (12) is partially applied to an end of the lead frame (8).