Stress Patterns Between Stacked Patterns in Non-Volatile Memory
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Solution Overview
Problem
Conventional EEPROMs suffer from unfavorable electrical performance, such as low reading current, unsatisfactory transconductance, slow programming speed, and short data retention time, along with complex manufacturing processes that deteriorate production efficiency.
Innovation Solution
A non-volatile memory structure and array that incorporates stress patterns made of tensile or compressive stress materials between stacked patterns, which include a charge storage layer of doped polysilicon or silicon nitride, and a dielectric layer that applies stress to the substrate, replacing conventional silicon oxide isolation patterns to enhance electrical performance and simplify manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon oxide isolation patterns are disposed above the doped regions to isolate doped regions or separate adjacent word lines, then isolation function is achieved, but manufacturing complexity increases and production efficiency deteriorates
Solution Approach 1:
The patent merges the isolation pattern material with the stress material by using the same material (silicon nitride) for both purposes. The isolation patterns are formed as part of the stress material deposition process, eliminating the need for separate isolation pattern fabrication steps while maintaining effective electrical isolation between doped regions and word lines.
2Reliability
If complicated manufacturing methods such as lift-off method are used to fabricate silicon oxide isolation patterns, then isolation structures are formed, but production efficiency and yield rate deteriorate
Solution Approach 1:
The patent extracts the isolation pattern fabrication step from the manufacturing process by using silicon nitride isolation patterns that are formed simultaneously with the stress material layers. This eliminates the need for separate lift-off processes and complex multi-step isolation pattern fabrication, thereby improving production efficiency and yield rate while maintaining effective isolation structure formation.
3Ease of manufacture
If conventional EEPROM structure with silicon oxide isolation patterns is used, then manufacturing is simpler, but electrical performance such as reading current, transconductance, programming speed, and data retention is unfavorable
Solution Approach 1:
The patent employs silicon nitride as a composite material that simultaneously provides isolation functionality and stress-induced electrical performance enhancement. The silicon nitride isolation patterns serve dual purposes: electrical isolation and applying mechanical stress to the channel region, thereby improving reading current, transconductance, programming speed, and data retention while maintaining manufacturing simplicity.
Solution Approach 2:
The patent changes the material parameter from silicon oxide to silicon nitride for the isolation patterns. This material substitution introduces tensile or compressive stress depending on the doping type, which modifies the electrical parameters of the transistor (mobility, threshold voltage) and thereby enhances reading current, transconductance, programming speed, and data retention characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution results in improved electrical performance with high reading current, favorable transconductance, fast programming speed, and long data retention, while simplifying the manufacturing process and increasing production efficiency.
Implementation Method 1
the stress patterns apply stresses to the substrate, thus permitting the non-volatile memory structure and the array thereof to have great electrical performance
Data Source
AI summary
A non-volatile memory structure including a substrate, stacked patterns and stress patterns is provided. The stacked patterns are disposed on the substrate. Each of the stacked patterns includes a charge storage structure and a gate from bottom to top. Here, the charge storage structure at least includes a charge storage layer. The stress patterns are disposed on the substrate between the two adjacent stacked patterns, respectively.