Stress Pulse Repair of Short-Type Defective Memory Cells
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Solution Overview
Problem
In semiconductor memory devices, short-type defective memory cells, also known as leaky cells, cause data corruption and require costly repairs by replacing both the leaky cell and normal cells sharing the same bit or word line, leading to inefficiencies in data storage and processing.
Innovation Solution
The implementation of a method to change short-type defective memory cells to open-type defective memory cells using stress pulses, which isolates the defective cells without affecting normal cells, thereby preventing current leakage and allowing normal operations to continue without repairing shared cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If short-type defective memory cells are repaired by replacing both defective and normal cells sharing the same bit or word line, then data corruption is prevented, but repair cost and circuit area increase
Solution Approach 1:
The patent segments the memory array into independently controllable blocks by introducing block select lines (BSL0, BSL1) that can selectively activate specific word line blocks. This allows the defective memory cell to be isolated in its own block, preventing the need to replace entire rows or columns. The block segmentation enables targeted repair operations that affect only the minimal necessary circuit area while maintaining data integrity in the segmented blocks.
Solution Approach 2:
The patent extracts the defective memory cell from the shared bit/word line context by using block select lines to isolate it in a dedicated block. The open-type defective cell is then configured to have zero current flow, effectively removing its harmful effect from the shared lines without physically replacing it or affecting normal cells on the same lines. This extraction principle allows repair without expanding circuit area.
2Loss of time
If short-type defective memory cells are isolated using stress pulses, then repair time and cost are minimized, but the method complexity increases
Solution Approach 1:
The patent implements self-service by integrating the stress pulse generation and application functionality directly into the existing memory device structure. The block select lines and word line control circuits that already exist for normal operation are repurposed to generate and apply stress pulses during repair mode. This eliminates the need for external complex test equipment, allowing the device to perform its own repair operation quickly without adding significant circuit complexity.
Solution Approach 2:
The patent makes the memory control circuits universal by enabling them to perform both normal memory operations and repair operations through the same block select lines and control logic. The word line control circuit can function as both a normal word line driver and a stress pulse generator depending on the operational mode. This multi-functionality reduces the need for separate dedicated repair circuits, minimizing added complexity while enabling rapid repair operations.
3Object-generated harmful factors
If stress pulses are applied to change defective cells to open-type, then current leakage is prevented, but normal cells may be affected
Solution Approach 1:
The patent applies local quality by restricting the stress pulse application to only the specific block containing the defective memory cell through block select line control. When BSL0 is activated, only the block associated with BSL0 receives the stress pulse, while other blocks remain unaffected. This localized approach ensures that normal cells in other blocks continue to operate reliably without being exposed to potentially harmful stress pulses, while still achieving the goal of preventing current leakage from the defective cell.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes repair time, cost, and circuit area by isolating the defective cells, ensuring that only the leaky cells are repaired, thus improving the operational characteristics of semiconductor memory devices.
Implementation Method 1
a first test circuit configured to apply a stress pulse to a first selection line coupled to a defective memory cell among the plurality of memory cells during a first test period
Data Source
AI summary
Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a plurality of first lines; a plurality of second lines; a plurality of memory cells disposed in respective intersection regions between the plurality of first lines and the plurality of second lines; a first test circuit configured to apply a stress pulse to a first selection line coupled to a defective memory cell among the plurality of memory cells during a first test period, in response to a first test control signal, the first selection line including any one of the plurality of first lines; and a control unit configured to generate the first test control signal based on a first test mode signal.