Organosilicon Stress Release Layer for 3D Memory Substrate Flatness
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Solution Overview
Problem
Existing three-dimensional semiconductor memory devices face challenges in maintaining substrate flatness and preventing warpage during the etching process, which affects the accuracy of photolithography and can lead to process failures such as arcing due to stress exerted by hard mask layers and stress layers.
Innovation Solution
Incorporating a stress release layer made of organosilicon polymer with a higher carbon concentration than the interlayer insulating layer, which reduces stress and maintains the substrate flatness by acting as a damper between the hard mask layer and the substrate, thereby improving the accuracy of photolithography and preventing arcing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a hard mask layer and stress layer are used in the etching process, then the etching accuracy is improved, but substrate warpage and stress increase leading to photolithography accuracy degradation and arcing failures
Solution Approach 1:
A stress release layer made of organosilicon polymer is introduced as an intermediary between the substrate and the hard mask layer. This stress release layer absorbs and dissipates the stress exerted by the hard mask layer during etching, preventing substrate warpage that would otherwise degrade photolithography accuracy. The stress release layer acts as a buffer that maintains substrate flatness while allowing the hard mask layer to perform its etching function.
Solution Approach 2:
The stress release layer is designed with specific material parameters - organosilicon polymer composition with controlled carbon concentration (20-40 at %) and porosity - to optimize its stress absorption capability. By adjusting these parameters, the layer can effectively counteract the stress from the hard mask layer without interfering with the etching process, thus resolving the contradiction between etching accuracy and photolithography accuracy.
2Manufacturing precision
If a hard mask layer is applied for precise etching, then etching precision is improved, but stress-induced arcing and process failures occur
Solution Approach 1:
The stress release layer is applied beforehand, before the hard mask layer is deposited, to create a cushioning effect. This pre-positioned stress absorption layer prevents the buildup of harmful stress that would lead to arcing and process failures during the etching process. By cushioning the stress in advance, the system can maintain high etching precision without suffering from stress-induced failures.
3Shape
If stress layers are added to compensate for substrate warpage, then substrate flatness is improved, but device complexity and process steps increase
Solution Approach 1:
The stress release layer is merged with the existing interlayer insulating layer structure, combining stress management functionality with the insulating layer. This integration approach maintains substrate flatness without adding separate, independent stress compensation layers, thereby reducing overall device complexity while still achieving the desired substrate flatness for accurate photolithography.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of the organosilicon polymer stress release layer effectively reduces substrate warpage and stress, enhancing the accuracy of the photolithography process and preventing process failures like arcing, thus improving the reliability of the semiconductor device fabrication.
Implementation Method 1
a stress release layer provided on the mold layer, the stress release layer including organosilicon polymer
Data Source
AI summary
Disclosed are a three-dimensional semiconductor memory device and an electronic system including the same. A semiconductor device includes a substrate, a cell array structure including a plurality of electrodes stacked on the substrate, a vertical channel structure that penetrates the cell array structure and is connected to the substrate, a conductive pad in an upper portion of the vertical channel structure, an interlayer insulating layer on the cell array structure, a bit line on the cell array structure, a bit line contact electrically connecting the bit line to the conductive pad, and a first stress release layer between the cell array structure and the bit line on a top surface of the interlayer insulating layer. The first stress release layer includes organosilicon polymer, and a carbon concentration of the first stress release layer is higher than that of the interlayer insulating layer.