Stress Releasing Layer for 3D IC TSV Reliability
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Solution Overview
Problem
In 3D integrated circuit manufacturing, the scaling down of through-silicon vias (TSVs) leads to severe thermal-mechanical stress, causing cracks and device failure due to the mismatch of thermal expansion coefficients between conductive materials and semiconductor materials.
Innovation Solution
A stress releasing layer is formed around the through holes in the 3D integrated circuit structure to mitigate the mechanical stress caused by conductive materials, improving the performance of MOSFET devices and overall 3D integrated circuits by reducing thermal expansion mismatch-induced stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive materials are filled to form TSVs in 3D integrated circuits, then interconnection functionality is improved, but thermal-mechanical stress increases causing cracks and device failure
Solution Approach 1:
A stress releasing layer is introduced as an intermediary between the conductive material layer and the semiconductor device. This layer acts as a buffer to absorb and distribute the thermal-mechanical stress generated during cooling, preventing direct stress transmission to the semiconductor device and interconnection structures, thereby reducing cracks and device failure while maintaining TSV interconnection functionality
2Productivity
If TSV sizes are scaled down to improve integration density, then 3D integrated circuit performance is improved, but thermal-mechanical stress concentration increases
Solution Approach 1:
The stress releasing layer is selectively applied in the regions surrounding the scaled-down TSVs, providing localized stress management where it is most needed. This allows the TSVs to maintain their small size for high integration density while the locally applied stress releasing layer compensates for the increased stress concentration inherent in smaller, more densely packed vias
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of a stress releasing layer effectively reduces mechanical stress, enhancing the performance and reliability of 3D integrated circuits by preventing cracks and device failures associated with thermal-mechanical stress.
Implementation Method 1
the mismatch of thermal expansion coefficients between conductive materials and semiconductor materials
Implementation Method 2
part of the stress caused by the mismatch of coefficient of thermal expansion (CTE) between the conductive material in the via and the semiconductor material surrounding the via can be released by forming a stress releasing layer in the via
Data Source
AI summary
A 3D integrated circuit structure comprises a first chip, wherein the first chip comprises: a substrate; a semiconductor device formed on the substrate and a dielectric layer formed on both the substrate and the semiconductor device; a conductive material layer formed within a through hole penetrating through both the substrate and the dielectric layer; a stress releasing layer surrounding the through hole; and a first interconnecting structure connecting the conductive material layer with the semiconductor device. By forming a stress releasing layer to partially release the stress caused by the conductive material in the via, the stress caused by mismatch of CTE between the conductive material and the semiconductor (for example, silicon) surrounding it can be reduced, thereby enhancing the performance of the semiconductor device and the corresponding 3D integrated circuit consisting of the semiconductor devices.