Patterned Stress-Relief Layer for Copper Metallization Warpage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The introduction of copper metallization in semiconductor devices leads to increased die bow/warpage and residual stress, resulting in voids in solder connections and potential early failure due to uneven solder distribution, which complicates electrical and thermal properties and reliability.
Innovation Solution
A stress relieving layer or layer stack with a patterned surface topography, comprising materials like polymers, aluminum-copper alloys, or nitrides, is applied over the semiconductor body to absorb stress and reduce bow/warpage, featuring openings arranged in regular or irregular patterns to provide a planar surface for metal layers that fill these openings, thereby reducing mechanical stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper metallization is used in the semiconductor device, then the on-state resistance is reduced, but die bow/warpage and residual stress increase
Solution Approach 1:
The stress relieving layer is divided into multiple discrete openings rather than a continuous layer. This segmentation allows the metal layers to fill the openings and create localized stress relief zones, reducing overall die bow while maintaining electrical connectivity through the openings.
Solution Approach 2:
The stress relieving layer is designed with a porous structure containing multiple openings. This porous configuration allows the layer to absorb and distribute stress throughout the die structure, preventing excessive bowing while maintaining mechanical integrity and electrical functionality.
2Reliability
If copper metallization is used in the semiconductor device, then the on-state resistance is reduced, but residual stress within the die increases
Solution Approach 1:
The continuous stress relieving layer is segmented into discrete openings, creating multiple localized stress relief zones. This segmentation distributes the residual stress throughout the die rather than concentrating it in one area, reducing overall stress accumulation.
Solution Approach 2:
The porous structure of the stress relieving layer with multiple openings provides pathways for stress dissipation. The void spaces within the porous structure allow the material to accommodate thermal expansion and contraction, reducing residual stress buildup during temperature cycling.
3Shape
If a stress relieving layer is added to reduce die bow, then the die bow is reduced, but the device complexity increases
Solution Approach 1:
The stress relieving layer is implemented as a porous structure with openings rather than a solid continuous layer. This porous configuration reduces the amount of material required and simplifies the manufacturing process compared to adding a complete additional layer, while still providing effective stress relief.
Solution Approach 2:
The stress relieving layer with openings serves multiple functions simultaneously: it provides stress relief, maintains electrical connectivity through the openings, and allows for subsequent metal layer deposition. This multi-functionality reduces the need for additional separate structures, simplifying the overall device architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The stress relieving layer effectively reduces die bow/warpage and mechanical stress, enhancing the reliability and stability of semiconductor packages by distributing stress evenly and preventing solder voids during temperature cycling.
Implementation Method 1
The stress relieving layer or layer stack absorbs at least some of the stress imparted by the metal layer or layer stack during temperature cycling and/or residual stress stored within the metal layer or layer stack
Implementation Method 2
the stress relieving layer or layer stack absorbs at least some of the stress imparted by the metal layer or layer stack during temperature cycling
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A semiconductor device includes a semiconductor body, a stress relieving layer or layer stack disposed over at least part of the semiconductor body, the stress relieving layer or layer stack comprising a plurality of openings which yield a patterned surface topography for the stress relieving layer or layer stack, and a metal layer or layer stack formed on the stress relieving layer or layer stack and occupying the plurality of openings in the stress relieving layer or layer stack. The patterned surface topography of the stress relieving layer or layer stack is transferred to a surface of the metal layer or layer stack facing away from the semiconductor body. The stress relieving layer or layer stack has a different elastic modulus than the metal layer or layer stack over a temperature range.