Stress-Resistant Bonding Bump Structure for Semiconductor Dies

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Solution Overview

Problem

Semiconductor dies are susceptible to stress-induced structural damage during handling processes such as C4 bonding and wirebonding, leading to deformation and potential failure.

Innovation Solution

The formation of connection pad-and-via structures with a bump via portion laterally offset from the connection via structure, which distributes mechanical stress across a larger area, enhancing stress resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional bonding structures are used, then electrical connection is provided, but stress-induced structural damage occurs during handling processes

Engineering Contradiction:

Improvestress resistanceVSAvoidstructural integrity

Core Design Contradiction:

ReliabilityVSStrength

Solution Approach 1:

The bonding structure is segmented into multiple components: a connection pad, a via structure, and a bump structure. The via structure is further divided into a via body and a bump via portion. This segmentation allows the stress to be distributed across multiple elements rather than concentrated at a single point, thereby improving stress resistance while maintaining structural integrity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The bump via portion is laterally offset from the connection via structure, creating a localized stress distribution pattern. This local quality change means that the stress is not uniformly distributed but rather concentrated in specific areas where the offset geometry provides stress relief, enhancing the overall stress resistance of the bonding structure.

Inventive Principle:

Principle #3Local quality

2Reliability

If the bump via portion is laterally offset from the connection via structure, then mechanical stress is distributed across a larger area, but structural complexity increases

Engineering Contradiction:

ImprovedurabilityVSAvoidbonding structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The bump via portion is nested within or adjacent to the connection via structure, with the bump via portion laterally offset from the via body. This nesting arrangement allows the complex geometry to be achieved within a compact footprint, distributing stress across a larger area while minimizing the overall increase in device complexity.

Inventive Principle:

Principle #7Nested doll (Nesting)

Data Source

PatentUS20250316632A1Semiconductor die including stress-resistant bonding structures and methods of forming the same

Publication Date: 2025.10.09 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor die including mechanical-stress-resistant bump structures is provided. The semiconductor die includes dielectric material layers embedding metal interconnect structures, a connection pad-and-via structure, and a bump structure including a bump via portion and a bonding bump portion. The entirety of a bottom surface of the bump via portion is located within an area of a horizontal top surface of a pad portion of the connection pad-and-via structure.