Stress-Resistant Bonding Bump Structure for Semiconductor Dies

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Solution Overview

Problem

Semiconductor dies are prone to structural damage due to mechanical stress during handling processes such as C4 bonding or wirebonding, which can lead to deformation and reliability issues.

Innovation Solution

The formation of stress-resistant bonding structures, including connection pad-and-via structures and bump structures, where the bump via portion is laterally offset from the connection via structure, allowing for the absorption of mechanical stress. This is achieved through specific geometrical configurations and material deposition processes within dielectric material layers, enhancing the semiconductor die's resistance to stress-induced damage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If bonding structures are formed for electrical connection, then electrical connectivity is achieved, but mechanical stress causes structural damage and deformation

Engineering Contradiction:

Improvestructural integrityVSAvoidmechanical stress damage

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies beforehand cushioning by forming a stress-resistant structure comprising a first via structure and a second via structure that are laterally offset from each other. This offset configuration creates a cushioning effect that absorbs and distributes mechanical stress before it can cause damage to the bonding structures, thereby preventing structural damage while maintaining electrical connectivity

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The patent uses an intermediary approach by introducing a stress-resistant structure as a mediator between the bonding structures and the external mechanical stress. This intermediate structure absorbs the harmful mechanical stress through its laterally offset via configuration, protecting the underlying bonding structures from damage while allowing electrical connection to function

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If laterally offset via structures are formed to absorb stress, then stress resistance is improved, but manufacturing complexity increases

Engineering Contradiction:

Improvestress resistanceVSAvoidbonding structure configuration

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the stress-resistant structure into separate first via structure and second via structure components that are laterally offset. This segmentation allows each via to be formed and positioned independently, making the complex offset configuration more manageable in terms of manufacturing while achieving the desired stress resistance through the distributed via arrangement

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS11887955B2Semiconductor die including stress-resistant bonding structures and methods of forming the same

Publication Date: 2024.01.30 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor die including mechanical-stress-resistant bump structures is provided. The semiconductor die includes dielectric material layers embedding metal interconnect structures, a connection pad-and-via structure, and a bump structure including a bump via portion and a bonding bump portion. The entirety of a bottom surface of the bump via portion is located within an area of a horizontal top surface of a pad portion of the connection pad-and-via structure.