Stress-Engineered Semiconductor Logic Memory Manufacturing
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Solution Overview
Problem
The existing methods for manufacturing semiconductor integrated circuits with logic and memory array parts face challenges in enhancing transistor performance and preventing damage to field effect transistors, leading to deterioration of memory retention characteristics and difficulties in forming openings for local interconnects.
Innovation Solution
A method involving the formation of insulation films with specific stresses on N-channel and P-channel field effect transistors, including selective removal and ion implantation steps to manage stress and prevent damage, allowing for enhanced transistor performance and improved manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If insulation films with tensile stress are formed on N-type FET regions and compressive stress films on P-type FET regions to enhance transistor performance, then field effect transistor performance is improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent applies different stress conditions to different regions: tensile stress insulation films are formed on N-type FET regions while compressive stress insulation films are formed on P-type FET regions. This local differentiation enhances transistor performance by optimizing carrier mobility in each region according to its specific electrical characteristics, resolving the contradiction between performance improvement and process complexity through targeted regional treatment.
Solution Approach 2:
The manufacturing process is segmented into distinct stages: forming tensile stress insulation films on N-type FET regions, then forming compressive stress insulation films on P-type FET regions. This segmentation allows independent optimization of each transistor type without interfering with the other, managing complexity through structured process division while achieving performance enhancement for both N-type and P-type FETs.
2Ease of manufacture
If existing manufacturing methods are used for memory array parts, then production can proceed with standard processes, but field effect transistors may be damaged leading to deterioration of memory retention characteristics
Solution Approach 1:
The patent applies preliminary protective measures by forming appropriate stress insulation films on FET regions before subsequent manufacturing steps. Tensile stress films on N-type FETs and compressive stress films on P-type FETs are established in advance to prevent damage during later processing, thereby preserving memory retention characteristics while allowing standard production processes to continue.
Solution Approach 2:
The stress insulation films are formed preliminarily before critical manufacturing steps that could damage FETs. By establishing the protective stress structure in advance, the patent ensures FET integrity is maintained throughout subsequent processing, preventing deterioration of memory retention characteristics while maintaining ease of manufacture through integrated process flow.
3Ease of manufacture
If existing manufacturing methods are used, then production can continue with current processes, but openings for local interconnects cannot be formed without damaging transistors
Solution Approach 1:
The stress insulation films are formed preliminarily to create a protective structure that enables subsequent opening formation for local interconnects. The tensile stress films on N-type FETs and compressive stress films on P-type FETs are established before opening processes, allowing safe formation of interconnect structures without damaging underlying transistors, thus improving ease of operation while maintaining current production processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance of both N-channel and P-channel transistors, improves memory retention characteristics, and facilitates the formation of local interconnects without damaging the transistors, thereby improving the overall manufacturing efficiency and yield of semiconductor integrated circuits.
Implementation Method 1
applying ion implantation for relaxation of compressive stress to the third insulation film present on the upper side of the region of the N channel type field effect transistor which constitutes the memory array part
Implementation Method 2
a technology of enhancing the performance by increasing the mobility through the use of a film stress has been paid attention to
Data Source
AI summary
A method of manufacturing a semiconductor integrated circuit including a logic part and a memory array part, the logic part having N-type and P-type FETs, and the memory array part having N-type and P-type FETs, includes the steps of forming N-type and P-type FETs constituting the logic part and the memory array part, thereafter sequentially forming a first insulation film having a tensile stress and a second insulation film on the whole surface, selectively removing the second insulation film and the first insulation film present on the upper side of the region of the P-type FET constituting the logic part, then forming a third insulation film having a compressive stress on the whole surface, and thereafter selectively removing the third insulation film present on the upper side of the region of the N-type FET constituting the logic part and the third insulation film present on the upper side of the regions of the N-type and P-type FETs constituting the memory array part.