Stress Test for Grown Bad Blocks in Non-Volatile Memory

The patent applies preliminary action by performing stress tests on memory blocks before they are fully programmed or during idle periods. The controller identifies candidate blocks and applies enhanced stress patterns (such as repeated program-erase cycles with elevated voltages) to accelerate defect manifestation before the blocks are put into normal service, thereby detecting potential grown bad blocks without disrupting ongoing memory operations.

The patent implements continuity of useful action by integrating stress testing into the background garbage collection process and idle time periods. Instead of stopping memory operations to perform defect detection, the controller continuously monitors and stresses memory blocks during normal operation, ensuring that defect detection occurs without interrupting data processing or storage operations.

The patent applies partial action by selecting only candidate blocks that meet specific criteria (such as blocks that have been erased a certain number of times or blocks showing early signs of degradation) for stress testing, rather than testing all memory blocks. This selective approach reduces the overall testing time while maintaining high detection accuracy for blocks most likely to develop defects.

The patent implements periodic action by performing stress tests at scheduled intervals based on memory block usage patterns, erase counts, or detected degradation trends. Instead of continuous testing of all blocks, the controller periodically selects candidate blocks for stress testing based on their operational history and risk profiles, optimizing the balance between detection accuracy and time consumption.

The patent applies segmentation by dividing the memory array into smaller sub-arrays or blocks when searching for short circuits. The controller applies stress patterns to specific segments independently, allowing parallel processing and faster localization of defects. By segmenting the search space, the system can quickly identify which sub-array contains a short circuit without having to test the entire memory array sequentially.

The patent implements feedback by using the results from initial stress tests to guide subsequent testing steps. When a short circuit is detected in a particular block, the controller uses this information to focus subsequent divide-and-conquer searches on specific word lines or bit lines within that block, rapidly narrowing down the exact location of the defect based on feedback from each testing iteration.