Stress-Engineered Thin-Film Transistors for Higher Carrier Mobility
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Solution Overview
Problem
Thin film transistors (TFTs) face challenges in enhancing on-current due to limitations in mechanical stress induction methods, which affect the mobility and performance of semiconductor channels in CMOS circuitry and ferroelectric memory cells.
Innovation Solution
The introduction of metallic liners that induce compressive or tensile stress in the end portions of semiconducting material layers, either through deposition or dopant implantation, to create mechanical stress within the semiconductor channel, thereby enhancing on-current and mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low temperature processing is used for oxide semiconductor TFTs, then previously fabricated FEOL devices are not damaged, but mechanical stress cannot be effectively induced to improve carrier mobility
Solution Approach 1:
The patent applies local quality by introducing stress only in specific regions (source and drain areas) rather than uniformly across the entire semiconductor layer. Different stress types (tensile in source/drain, compressive in channel) are applied locally to achieve both low-temperature compatibility and enhanced carrier mobility through localized lattice constant modification.
Solution Approach 2:
The patent changes physical parameters by implanting dopants with different atomic sizes into specific regions to induce mechanical stress. This parameter change (dopant concentration and type) allows stress induction at low temperatures, resolving the contradiction between temperature constraints and stress effectiveness.
2Productivity
If dopants are implanted to change lattice constant and generate mechanical stress, then carrier mobility is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by performing dopant implantation during the low-temperature processing stage before subsequent high-temperature steps. This timing allows the stress-induced mobility enhancement to be established early, while the implantation process itself is integrated into existing low-temperature fabrication flows, minimizing added complexity.
Solution Approach 2:
The patent uses local quality by implanting dopants selectively into source and drain regions rather than uniformly across the semiconductor layer. This localized approach achieves stress-induced mobility enhancement in critical areas while avoiding the complexity of uniform doping and reducing overall manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases the on-current and mobility of charge carriers in TFTs by altering the lattice constant of the semiconducting material layers, improving the performance of CMOS circuitry and ferroelectric memory cells.
Implementation Method 1
mechanically stressing the channel portion of TFTs using a metallic liner that induces compressive or tensile stress in the end portions of the semiconducting material layer
Implementation Method 2
implanting dopants to change the lattice constant and generate mechanical stress
Data Source
AI summary
A planar insulating spacer layer can be formed over a substrate, and a combination of a semiconducting material layer, a thin film transistor (TFT) gate dielectric layer, and a gate electrode can be formed over the planar insulating spacer layer. A dielectric matrix layer is formed thereabove. A source-side via cavity and a drain-side via cavity can be formed through the dielectric matrix layer over end portions of the semiconducting material layer. Mechanical stress can be generated between the end portions of the semiconducting material layer by changing a lattice constant of end portions of the semiconducting material layer. The mechanical stress can enhance the mobility of charge carriers in a channel portion of the semiconducting material layer.