Stress-Treated Gate Stacks for Low-Warpage FinFET Fabrication
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Solution Overview
Problem
Existing gate fabrication techniques and gate replacement processes in IC manufacturing are inadequate in addressing the warping and void/seam formation issues in gate structures due to residual stress in glue layers, leading to degraded performance and reliability of FinFETs as IC feature sizes shrink.
Innovation Solution
Implementing stress-treated glue layers with compressive or negligible tensile residual stress to reduce warping and void/seam formation in gate stacks, achieved through ion implantation or thermal processes, and hydrogen poisoning of glue sublayers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional gate fabrication techniques are used, then manufacturing simplicity is maintained, but gate structure warping and void/seam formation occur due to residual stress in glue layers
Solution Approach 1:
The patent applies preliminary action by performing stress treatment on the glue layer during the fabrication process, specifically through ion implantation or thermal processes, to reduce residual stress before subsequent processing steps. This prevents warping and void formation in advance, ensuring gate structure integrity without requiring complex post-processing corrections
Solution Approach 2:
The patent changes physical parameters of the glue layer through stress treatment processes. Ion implantation modifies the chemical composition and stress state of the glue layer, while thermal processes alter temperature parameters to reduce residual stress. These parameter changes transform the glue layer from a stress-prone state to a stable, low-stress state that prevents warping
2Productivity
If IC feature sizes are scaled down, then production efficiency increases and costs decrease, but gate structure warping and void formation become more severe
Solution Approach 1:
The patent applies preliminary anti-action by introducing stress treatment processes that counteract the residual stress in glue layers before it can cause warping or void formation. This is particularly critical for scaled-down features where even minor stress-induced deformations can cause manufacturing failures. The ion implantation and thermal processes create a compensating stress state that prevents the harmful warping effect
Solution Approach 2:
The patent modifies physical parameters of the glue layer through ion implantation and thermal treatment to achieve uniform stress distribution. This ensures that even as feature sizes shrink, the gate structure maintains uniform critical dimensions and proper morphology, preventing void and seam formation that would compromise manufacturing precision
3Manufacturing precision
If stress reduction techniques are applied to glue layers, then gate structure warping is minimized and uniformity is improved, but additional processing steps are required
Solution Approach 1:
The patent incorporates stress treatment as a preliminary step in the gate fabrication sequence, performing ion implantation or thermal processing on the glue layer before subsequent deposition and patterning steps. This timing ensures that the glue layer is stress-relieved in advance, preventing warping during later processing and eliminating the need for additional corrective steps
Solution Approach 2:
The stress treatment processes act as intermediary steps that mediate between glue layer deposition and subsequent gate structure formation. The ion implantation and thermal processes serve as intermediate treatments that modify the glue layer's stress state, creating a stable foundation for subsequent processing and ensuring uniform critical dimensions without requiring complex post-processing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The stress reduction techniques significantly minimize gate structure warping, ensuring uniform critical dimensions and enhancing the reliability and performance of FinFETs by preventing damage to the channel region.
Implementation Method 1
achieved through ion implantation or thermal processes
Implementation Method 2
achieved through ion implantation or thermal processes
Implementation Method 3
hydrogen poisoning of glue sublayers
Data Source
AI summary
Gate fabrication techniques are disclosed herein for providing gate stacks and/or gate structures (e.g., high-k/metal gates) with improved profiles (e.g., minimal to no warping, bending, bowing, and necking and/or substantially vertical sidewalls), which may be implemented in various device types. For example, gate fabrication techniques disclosed herein provide gate stacks with stress-treated glue layers having a residual stress that is less than about 1.0 gigapascals (GPa) (e.g., about −2.5 GPa to about 0.8 GPa). In some embodiments, a stress-treated glue layer is provided by depositing a glue layer over a work function layer and performing a stress reduction treatment, such as an ion implantation process and/or an annealing process in a gas ambient, on the glue layer. In some embodiments, a stress-treated glue layer is provided by forming at least one glue sublayer/metal layer pair over a work function layer, performing a poisoning process, and forming a glue sublayer over the pair.