Stress-Tuning Oxide Stack for 3D Wafer Bonding Alignment
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Solution Overview
Problem
Current 3D ICs face challenges with wafer warpage due to different fabricating processes for upper and lower wafers, leading to alignment issues and affected properties.
Innovation Solution
A semiconductor device is designed with a stress tuning structure on one wafer, comprising a first oxide layer and a second oxide layer with different refractive indices, which helps in controlling stress and improving bonding surface flatness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different kinds of wafers (logic wafers or DRAM wafers) are used for upper and lower wafers in 3D IC, then functional versatility is improved, but wafer warpage increases due to different fabricating processes
Solution Approach 1:
The patent applies parameter changes by modifying the physical and chemical properties of the oxide layers in the stress tuning structure. By controlling the refractive indices, thicknesses, and material compositions of the first and second oxide layers, the stress distribution within the wafer is adjusted to compensate for warpage caused by different fabricating processes on logic and DRAM wafers
Solution Approach 2:
The patent uses composite materials by creating a multi-layer stress tuning structure comprising different oxide materials with distinct refractive indices. This composite structure allows independent optimization of stress characteristics for each layer, enabling precise control over wafer shape while maintaining functional versatility of different wafer types
2Manufacturing precision
If stress tuning structure with multiple oxide layers is added to control wafer shape, then alignment precision is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the stress tuning function into multiple discrete oxide layers, each with specific refractive index characteristics. This segmentation allows independent control and optimization of stress parameters for each layer, achieving precise alignment control while maintaining manageable structural complexity through modular design
3Ease of manufacture
If wafer bonding is performed without stress control, then manufacturing process is simpler, but bonding quality deteriorates due to alignment errors
Solution Approach 1:
The patent applies preliminary action by implementing the stress tuning structure and performing stress control operations before the wafer bonding process. This preliminary stress management ensures that wafers are pre-adjusted to optimal alignment conditions, thereby improving bonding quality without significantly complicating the overall manufacturing process
Data Source
AI summary
A semiconductor device includes a first wafer and a second wafer. The first wafer includes a first substrate, a stress tuning structure and a first bonding structure. The stress tuning structure is disposed on the first substrate. The stress tuning structure includes a first oxide layer and a second oxide layer sequentially disposed on the first substrate, and a first refractive index of the first oxide layer is different from a second refractive index of the second oxide layer. The first bonding structure is disposed on the stress tuning structure. The second wafer includes a second substrate and a second bonding structure. The second bonding structure is disposed on the second substrate. The second bonding structure is bonded with the first bonding structure.