Stressed Standard Cell Gate-Cut Shapes for FinFET Delay Reduction
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Solution Overview
Problem
Standard cell design for Fin-FET technology is burdened by deep sub-micron stress and proximity effects, leading to inefficient layout and poor performance due to uncorrelated electrical characteristics and wasted layout area from mitigation strategies.
Innovation Solution
The method involves replacing candidate cells in a circuit model with stressed cells that include gate-cut and active-cut shapes, which are designed to create beneficial stresses, thereby improving the performance of combinatorial logic functions by reducing delay and enhancing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional unstressed cell design is used, then layout is simpler and manufacturing is easier, but delay is higher and speed is lower
Solution Approach 1:
The patent applies parameter changes by introducing stress conditions (tensile or compressive) to modify the electrical characteristics of the cell. This changes the operating parameters of the transistor channel, reducing delay and improving speed without fundamentally altering the cell structure.
Solution Approach 2:
The cell structure is segmented into distinct regions with different stress conditions. The first and second portions of the cell experience different stress states, allowing optimized performance in each region while maintaining overall cell functionality.
2Reliability
If stress mitigation strategies are applied, then electrical characteristics become more predictable, but layout area is wasted due to required open space distances
Solution Approach 1:
The patent converts the previously harmful stress effects into beneficial controls. By deliberately introducing stress conditions through controlled cell design, the electrical characteristics become more predictable and performance is improved, rather than trying to mitigate stress entirely.
Solution Approach 2:
Different portions of the cell are given different stress conditions tailored to their specific functional requirements. This local differentiation allows optimized electrical characteristics without requiring uniform spacing throughout the entire layout.
3Productivity
If continuous patterns are used without breaks, then layout density is higher, but neighboring devices experience undesired electrical characteristics
Solution Approach 1:
The cell design introduces localized stress regions that can be strategically positioned to affect only specific portions of the cell, allowing high layout density while controlling electrical effects to minimize impact on neighboring devices.
Solution Approach 2:
The cell is divided into segments with different stress characteristics, allowing the design to maintain continuity for high density while using segmentation to control and limit the propagation of electrical effects to adjacent cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces delay by at least half and improves speed by up to 25% compared to traditional unstressed cells, while maintaining logical function equivalence.
Implementation Method 1
employing a sub-micron stress effect, and, for each candidate, replacing a candidate cell with a stressed cell
Implementation Method 2
Using deep sub-micron stress effects and proximity effects to create a high performance standard cell
Data Source
AI summary
According to one general aspect, a method may include receiving a circuit model that includes logic circuits that are represented by respective cells. The method may include providing a timing adjustment to the circuit model. This providing may include determining one or more respective cells that are candidates for adjustment by employing a sub-micron stress effect, and, for each candidate, replacing a candidate cell with a stressed cell, wherein a candidate cell and stressed cell perform a same logical function. Each stressed cell may include: a gate electrode, a first gate-cut shape disposed to cut the gate electrode, wherein the first gate-cut shape is disposed upon a row-boundary, a second gate-cut shape disposed upon the row-boundary, a gate-cut break disposed between the first gate-cut shape and the second gate-cut shape, an active region, and an active-cut shape disposed to cut the active region.