Stressed-Channel CMOS Transistor Fabrication via Selective Stress Layering
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Solution Overview
Problem
Current methods for forming CMOS devices with stressed-channel NMOS and strained-channel PMOS transistors require numerous manufacturing steps, making them costly and inefficient.
Innovation Solution
A method that implants p-type dopants into an n-type silicon substrate, forms p-type source and drain regions, and then implants an n-type dopant through a non-conductive layer to create a stress layer, which is etch selective, allowing for the formation of stressed-channel NMOS and strained-channel PMOS transistors with reduced stress and strain introduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods are used to form stressed-channel NMOS and strained-channel PMOS transistors, then transistor performance can be improved, but the number of manufacturing steps increases and fabrication cost increases
Solution Approach 1:
The patent combines the formation of n-type and p-type source/drain regions into a single dual-ion implantation step, and merges the stress layer formation with the PMOS strain induction process. This integration reduces the total number of manufacturing steps while achieving both stressed-channel NMOS and strained-channel PMOS transistors, directly resolving the contradiction between improved transistor performance and reduced device complexity
Solution Approach 2:
The stress layer serves multiple functions: it induces strain in PMOS channel regions to improve hole mobility, and simultaneously provides stress to NMOS channel regions to enhance electron mobility. This multi-functionality allows a single process step to contribute to both NMOS and PMOS performance improvement, reducing the need for separate processing steps
2Reliability
If a stress layer is deposited to improve NMOS transistor performance, then electron mobility increases, but stress is also imparted to PMOS transistors which is not desirable
Solution Approach 1:
The patent applies local quality by selectively removing the stress layer from regions overlying PMOS transistors while retaining it over NMOS transistors. This is achieved through selective etching processes that exploit differences in etch selectivity between the stress layer material and underlying structures. The result is that NMOS devices receive the beneficial stress for enhanced electron mobility, while PMOS devices are protected from unwanted stress
Solution Approach 2:
The stress layer is segmented into different regions with different functionalities: one region retains the stress layer to provide stress to NMOS channels, while another region has the stress layer removed to prevent stress in PMOS channels. This spatial segmentation allows differential stress management for different transistor types on the same die
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes stress in PMOS transistors, introduces strain effectively, and reduces the number of fabrication steps, leading to improved transistor performance and reduced leakage current while maintaining high mobility.
Implementation Method 1
The method implants spaced-apart portions of the p-type single-crystal-silicon substrate region through the non-conductive layer with an n-type dopant
Implementation Method 2
anneals the p-type single-crystal-silicon substrate region after the stress layer has been formed to form an n-type source region and an n-type drain region
Implementation Method 3
This high temperature treatment, however, also increases the stress within the stress layer, which transmits the stress to the channel regions of the NMOS transistors
Implementation Method 4
The SiGe source and drain regions have a different lattice spacing than the single-crystal-silicon source and drain regions. The different lattice spacing, in turn, introduces strain to the channel regions of the PMOS transistors
Data Source
AI summary
A method of forming stressed-channel NMOS transistors and strained-channel PMOS transistors forms p-type source and drain regions before an n-type source and drain dopant is implanted and a stress memorization layer is formed, thereby reducing the stress imparted to the n-channel of the PMOS transistors. In addition, a non-conductive layer is formed after the p-type source and drain regions are formed, but before the n-type dopant is implanted. The non-conductive layer allows shallower n-type implants to be realized, and also serves as a buffer layer for the stress memorization layer.