Stressed Channel Layout Using Self-Aligned Diffusion Breaks
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Solution Overview
Problem
Conventional methods for incorporating stress in semiconductor devices face challenges in achieving consistent stress levels, particularly in multi-channel semiconducting nanostructures, leading to unfavorable hole and electron mobility, and require compromises in material selection that affect device performance.
Innovation Solution
The use of self-aligned single diffusion breaks with tailored liners and fill materials, such as dielectric materials like silicon nitride and silicon dioxide, to impart stress to the channel region without altering the composition of adjacent source and drain regions, allowing for improved stress consistency and mobility without additional channels or diffusion breaks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods are used to incorporate stress in semiconductor devices, then material selection compromises are required, but stress consistency and mobility are adversely affected
Solution Approach 1:
The patent divides the stress incorporation approach into separate components: self-aligned single diffusion breaks are formed independently in n-MOS and p-MOS regions, with different fill materials (tensile-stressed for n-MOS, compressive-stressed for p-MOS) deposited in separate steps. This segmentation allows each region to receive optimized stress treatment without compromising the other, achieving consistent stress levels across diverse device structures.
Solution Approach 2:
The patent applies different fill materials with specific stress characteristics to different locations: tensile-stressed dielectric material is deposited in n-MOS region diffusion breaks to enhance electron mobility, while compressive-stressed dielectric material is deposited in p-MOS region diffusion breaks to enhance hole mobility. This local customization of material properties achieves optimal stress consistency for each device type without requiring broad material compromises.
2Reliability
If additional channels or diffusion breaks are added to improve stress, then stress consistency may improve, but device complexity increases
Solution Approach 1:
The patent forms self-aligned single diffusion breaks before final device assembly, preparing the stress incorporation structures in advance. These pre-formed diffusion breaks are then filled with appropriate stress-inducing materials in subsequent steps. This preliminary preparation allows stress to be incorporated efficiently without requiring additional channels or complex multi-step diffusion processes, maintaining device simplicity while achieving consistent stress and improved mobility.
3Manufacturing precision
If as-deposited film characteristics are improved, then device performance may improve, but deposition challenges increase
Solution Approach 1:
The patent utilizes dielectric fill materials with inherently different stress states (tensile vs. compressive) as key parameters. By selecting materials with specific stress characteristics and controlling their deposition parameters, the patent achieves consistent stress incorporation in the channel regions. The self-aligned single diffusion break structure further controls stress distribution, allowing as-deposited film characteristics to be optimized for device performance while managing deposition challenges through precise parameter control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides consistently stressed channels with enhanced hole and electron mobility, increasing drive current and transistor performance by maintaining stress consistency across the channel region, even in complex geometries and orientations.
Implementation Method 1
the second self-aligned single diffusion break includes a compressive stressed fill material characterized by a compressive stress of greater than or about 350 MPa
Implementation Method 2
the dielectric liner material of the first liner has an etch rate that is different than an etch rate of the first fill material
Data Source
AI summary
The present technology includes semiconductor devices with improved stress in a channel region. The semiconductor device includes a substrate, a source region, a drain region, a channel region that includes at least one channel located between the source and the drain. Devices include a first gate region having a first self-aligned single diffusion break in a n-MOS region, and a second gate region includes having a self-aligned single diffusion break in a p-MOS region. The second self-aligned single diffusion break also contains a liner and a compressive stressed material, where the stressed metal fill exhibits a compressive stress of about 350 MPa or greater.