Stressed Channel FET With Source Drain Buffers
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Solution Overview
Problem
In semiconductor manufacturing, the close proximity of heavily doped source/drain stressor material to the channel region in FET devices leads to degradation of electrostatics, increased parasitic leakage, junction capacitance, and short channel effects, which hampers the performance of field effect transistors.
Innovation Solution
The introduction of vertical source/drain buffers between the channel and the embedded source/drain stressor material, which are lightly doped or undoped SiGe or SiC, reduces junction capacitance and leakage current while allowing for increased stress induction in the channel region by positioning the source/drain stressor material closer to the channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If heavily doped source/drain stressor material is positioned in close proximity to the channel region, then channel stress and mobility are enhanced, but junction capacitance and parasitic leakage increase
Solution Approach 1:
An lightly-doped or undoped buffer region is introduced between the heavily-doped source/drain stressor material and the channel region. This buffer acts as an intermediary that maintains the mechanical stress coupling to enhance channel mobility while electrically isolating the heavy doping from the channel, thereby reducing junction capacitance and parasitic leakage currents.
Solution Approach 2:
The source/drain region is segmented into multiple zones with different doping concentrations: a heavily-doped stressor region for mechanical stress, an lightly-doped or undoped buffer region for electrical isolation, and a lightly-doped extension region. This segmentation allows independent optimization of stress induction and electrical performance.
2Stress or pressure
If heavily doped source/drain stressor material is positioned in close proximity to the channel region, then channel stress is increased, but short channel effects and punchthrough are exacerbated
Solution Approach 1:
The lightly-doped buffer region serves as a mediator that transmits mechanical stress from the heavily-doped stressor to the channel while providing electrical isolation. This prevents the heavy doping from directly affecting the channel electrostatics, thereby mitigating short channel effects and punchthrough while maintaining beneficial channel stress.
Solution Approach 2:
Different regions of the source/drain structure are assigned different doping qualities: heavy doping in the stressor region for maximum stress induction, light or no doping in the buffer region adjacent to the channel for electrostatic control. This local differentiation allows simultaneous achievement of high channel stress and reduced short channel effects.
3Stress or pressure
If heavily doped source/drain material is placed close to the channel, then stress induction is maximized, but electrostatics of the FET device are degraded
Solution Approach 1:
The lightly-doped or undoped buffer region acts as an intermediary layer between the heavily-doped stressor material and the channel. This buffer maintains mechanical coupling for stress transmission while providing electrical isolation that preserves the electrostatics of the FET device, preventing degradation of threshold voltage control and subthreshold characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances channel mobility while minimizing leakage current and junction capacitance, thereby improving the overall performance of the FET devices.
Implementation Method 1
Mechanical stresses within a semiconductor device substrate may be used to modulate device performance. In this arrangement, hole mobility is enhanced when the channel is under compressive stress in the film direction and/or under tensile stress in a direction normal of the channel
Data Source
AI summary
A stressed channel field effect transistor (FET) includes a substrate; a gate stack located on the substrate; a channel region located in the substrate under the gate stack; source/drain stressor material located in cavities in the substrate on either side of the channel region; and vertical source/drain buffers located in the cavities in the substrate between the source/drain stressor material and the substrate, wherein the source/drain stressor material abuts the channel region above the source/drain buffers.