Stressed Channel Transistors With Segmented SiGe Trenches
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Solution Overview
Problem
Current transistors lack enhanced performance, necessitating the development of new structures and fabrication methods to improve their speed and gain.
Innovation Solution
The method involves forming a gate stack on a silicon layer with SiGe filled trenches on either side, separated by silicon regions, and creating source/drains that abut a channel region under the gate stack, inducing compressive stress to increase carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If SiGe regions are embedded to increase carrier mobility, then transistor performance is improved, but strain relief occurs reducing the stress effect
Solution Approach 1:
The SiGe structure is segmented into multiple regions: SiGe trenches embedded in the silicon layer, separated by silicon regions. This segmentation allows the SiGe to provide compressive stress to the channel while the intervening silicon regions prevent continuous strain relief, maintaining the stress effect across the channel region.
Solution Approach 2:
Different regions of the transistor structure are assigned different material compositions: SiGe is placed in trenches adjacent to the channel to provide compressive stress, while silicon regions are positioned between the SiGe trenches. This local differentiation optimizes each region's function - SiGe for stress induction and silicon for preventing strain relief.
2Speed
If new transistor structures are developed to improve performance, then speed and gain increase, but device complexity increases
Solution Approach 1:
The SiGe trenches are nested within the silicon layer, with the gate stack positioned above the silicon layer. This nested configuration integrates the stress-inducing SiGe regions into the existing transistor architecture without requiring separate external stress application mechanisms, thereby improving performance while limiting complexity increase.
Solution Approach 2:
The SiGe trenches are merged with the standard CMOS fabrication process flow, where trenches are etched into the silicon layer and filled with SiGe material during the same processing sequence used for source/drain formation. This merging of stress induction into the existing manufacturing process reduces the need for additional separate steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances transistor performance by increasing the mobility of majority carriers, thereby improving speed and gain while minimizing strain relief through reduced SiGe surface area.
Implementation Method 1
Silicon-Germanium (SiGe) has an increased crystal lattice spacing compared to silicon alone. By embedding SiGe regions on either side of silicon channel of a field effect transistor (FET) the channel region will be put in compressive stress.
Data Source
AI summary
A method of forming a field effect transistor and a field effect transistor. The method includes (a) forming gate stack on a silicon layer of a substrate; (b) forming two or more SiGe filled trenches in the silicon layer on at least one side of the gate stack, adjacent pairs of the two or more SiGe filled trenches separated by respective silicon regions of the silicon layer; and (c) forming source/drains in the silicon layer on opposite sides of the gate stack, the source/drains abutting a channel region of the silicon layer under the gate stack.