Stressed Crystalline Dielectric Layer for DRAM Leakage Reduction
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Solution Overview
Problem
Current dielectric materials in electronic memory devices, such as DRAM, face challenges in increasing storage capacity and reducing leakage currents while minimizing feature size, necessitating higher dielectric constants and improved crystalline states in dielectric layers.
Innovation Solution
A dielectric layer is fabricated in a crystalline state, specifically tetragonal, orthorhombic, or cubic, with stress induction to stabilize the crystalline structure, using transition metal oxides and dopants like silicon, aluminum, and rare earth elements, which enhances the dielectric constant and allows for miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the dielectric constant of the dielectric material is increased to enhance capacity and reduce feature area, then the storage capacity increases and feature size reduces, but leakage currents through the dielectric material may increase
Solution Approach 1:
The patent applies parameter changes by transitioning the dielectric material from an amorphous state to a crystalline state (specifically tetragonal, orthorhombic, or cubic crystal structures). This phase change fundamentally alters the material's electrical properties, achieving a higher dielectric constant while simultaneously reducing leakage currents through the modified crystal lattice structure.
Solution Approach 2:
The patent employs composite materials by combining transition metal oxides (such as hafnium oxide, zirconium oxide, or titanium oxide) with dopants including rare earth elements (lanthanum, cerium, praseodymium, neodymium, promethium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, or lutetium). This composite approach optimizes both the dielectric constant and leakage current characteristics.
2Quantity of substance
If high-k materials are used to increase the dielectric constant, then the dielectric constant increases, but the crystalline structure stability may be compromised without stress induction
Solution Approach 1:
The patent applies the counterweight principle by introducing mechanical stress (compressive or tensile) to counterbalance the inherent instability of the crystalline structure. This stress induction compensates for the structural weaknesses that arise from using high-k dielectric materials, thereby stabilizing the crystal phase and maintaining its properties during device operation.
Solution Approach 2:
The patent utilizes parameter changes by controlling the crystal structure type (tetragonal, orthorhombic, or cubic) and applying mechanical stress as a controlling parameter. These parameter adjustments enable the dielectric material to maintain both high dielectric constant and structural stability simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The stressed crystalline dielectric layer improves the dielectric constant, enabling increased storage capacity and reduced leakage currents, facilitating the miniaturization of electronic components like transistors and capacitors in memory devices.
Implementation Method 1
The dielectric layer is in a crystalline state and stressed
Implementation Method 2
The dielectric layer is in a crystalline state and stressed
Data Source
AI summary
A method of fabricating an integrated circuit with a dielectric layer on a substrate is disclosed. One embodiment provides forming the dielectric layer in an amorphous state on the substrate, the dielectric layer having a crystallization temperature; a doping the dielectric layer; a forming of a covering layer on the dielectric layer at a temperature being equal to or below the crystallization temperature; and a heating of the dielectric layer to a temperature being equal to or greater than the crystallization temperature.