Stressed Interlayer Dielectric Void Reduction via Etch Control Layer
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Solution Overview
Problem
In highly scaled transistor elements, conventional techniques for forming stressed dielectric layers suffer from reduced efficiency and non-uniformities during patterning and contact opening formation, leading to voids and reduced strain transfer, which compromises transistor performance.
Innovation Solution
A technique is introduced where a material layer with enhanced gap fill capabilities is deposited to smooth the surface topography after the first stress-inducing layer, allowing for reliable filling of spaces between gate electrode structures and enabling the deposition of a subsequent highly stressed material with improved conformality, thereby reducing voids and irregularities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a thin insulating layer is used to separate the gate electrode from the channel region to reduce channel length and increase operating speed, then the operating speed of the integrated circuits is improved, but short channel effects occur that reduce controllability of channel conductivity
Solution Approach 1:
The patent modifies the physical and chemical parameters of the channel region by introducing strain through stressed dielectric layers. By changing the stress state (tensile or compressive) in the channel region, the charge carrier mobility is enhanced, allowing the transistor to maintain high speed performance while mitigating short channel effects through strain-induced mobility improvement rather than simply reducing dimensions further.
Solution Approach 2:
The patent transitions from controlling transistor performance solely through dimensional scaling (length reduction) to utilizing a different dimension - the stress state of the dielectric layer. By introducing a vertical stress component through specially engineered dielectric layers with controlled internal stress, the patent addresses short channel effects without further reducing the already minimal channel length, thus maintaining controllability while preserving speed.
2Reliability
If PECVD silicon nitride is deposited with high intrinsic stress to enhance transistor performance, then the drive current capability is improved, but voids and material irregularities occur due to limited conformal deposition capabilities
Solution Approach 1:
The patent divides the single high-stress dielectric layer into multiple segments or layers with different stress characteristics. By using a stack of dielectric layers with varying internal stresses (some tensile, some compressive), the patent achieves net stress induction in the channel region while distributing the deposition process across multiple conformal layers, thereby avoiding void formation that would occur in a single thick non-conformal layer.
Solution Approach 2:
The patent employs a composite dielectric layer stack consisting of multiple dielectric materials with different stress properties. By combining materials that exhibit tensile stress with those exhibiting compressive stress in a layered configuration, the patent achieves the desired net stress effect on the transistor channel while maintaining conformal deposition across all layers, thus eliminating voids and material irregularities.
3Reliability
If the thickness of the stress-inducing dielectric layer is increased to improve strain induction, then the charge carrier mobility is enhanced, but voids and deposition irregularities increase due to pronounced surface topography
Solution Approach 1:
The patent segments the thick stress-inducing layer into multiple thinner conformal layers. Each thin layer deposits uniformly without creating significant surface topography variations, yet collectively they provide the necessary strain induction. This segmented approach maintains charge carrier mobility enhancement while eliminating deposition irregularities and voids.
Solution Approach 2:
The patent uses a composite stack of multiple dielectric layers with different thicknesses and stress characteristics. This composite structure distributes the total stress induction across several conformal layers, preventing the formation of voids and surface irregularities that would result from depositing a single thick non-conformal layer, while still achieving the required strain for enhanced charge carrier mobility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the applicability of dual stress liner techniques to devices with gate lengths of 50 nm or less, improving strain induction and reducing yield loss by ensuring consistent stress distribution and increased stress transfer, thus enhancing transistor performance.
Implementation Method 1
effective stress engineering, may be accomplished by individually adjusting the internal stress of these layers
Implementation Method 2
creating tensile or compressive strain therein, which results in a modified mobility for electrons and holes
Implementation Method 3
typically, the contact etch stop layer is formed by plasma enhanced chemical vapor deposition (PECVD) processes
Implementation Method 4
an etch process may be performed in order to remove a portion of the layers
Data Source
AI summary
By forming an etch control material with increased thickness on a first stressed dielectric layer in a dual stress liner approach, the surface topography may be smoothed prior to the deposition of the second stressed dielectric material, thereby allowing the deposition of an increased amount of stressed material while not contributing to yield loss caused by deposition-related defects.