Stressed Dielectric Layer Stack for Transistor Strain Transfer
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Solution Overview
Problem
In highly scaled semiconductor devices, the efficiency of strain-inducing mechanisms and uniformity of contact openings are compromised due to limitations in conformal deposition processes, leading to non-uniformities and defects in stressed dielectric layers, which affect transistor performance.
Innovation Solution
A dual stress liner approach is adopted, where two differently stressed dielectric layers are formed using a multi-step deposition process to enhance scalability, with additional stressed dielectric material deposited to improve uniformity and strain transfer, while respecting device geometry and process constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single stress-inducing layer is formed above transistors using conformal deposition, then the layer provides strain to the channel region, but the deposition process creates non-uniformities and defects in highly scaled devices
Solution Approach 1:
The patent divides a single stress-inducing layer into multiple separately deposited layers (first stress-inducing layer and second stress-inducing layer). Each layer is deposited independently with controlled thickness and stress characteristics, allowing better uniformity and reduced defects in highly scaled devices while maintaining the overall strain effect on the channel region.
2Reliability
If the thickness of stress-inducing layers is increased to improve strain effect, then transistor performance increases, but patterning non-uniformities and defects worsen
Solution Approach 1:
Instead of depositing one thick stress-inducing layer that causes patterning defects, the patent segments the total thickness into multiple thinner layers. The first stress-inducing layer has a first thickness and the second stress-inducing layer has a second thickness, with each layer being thin enough to deposit conformally without creating severe non-uniformities during subsequent patterning, while the combined thickness provides sufficient strain for improved transistor performance.
Solution Approach 2:
The patent introduces an additional dimension in the layer stack by adding multiple stress-inducing layers at different positions above the transistor. This vertical stacking approach allows the total stress effect to be distributed across multiple interfaces and thicknesses, improving both the strain effectiveness and the uniformity of the deposition and patterning processes.
3Adaptability or versatility
If differently stressed dielectric layers are formed for different transistor types, then strain engineering effectiveness improves, but process complexity and deposition constraints increase
Solution Approach 1:
The patent applies different stress characteristics to different regions by forming a first stress-inducing layer with first stress characteristics above first transistors and a second stress-inducing layer with second stress characteristics above second transistors. This local differentiation allows optimized strain engineering for different transistor types (e.g., N-channel and P-channel) while using a systematic multi-layer approach that manages process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces patterning-induced non-uniformities and enhances strain-inducing mechanisms, improving transistor performance without affecting other transistor types, and allows for increased deposition of stressed material within process limits, enabling self-scaling for further device geometries.
Implementation Method 1
Enhanced stress transfer in an interlayer dielectric by using an additional stress layer above a dual stress liner
Implementation Method 2
creating tensile or compressive strain therein, which results in a modified mobility for electrons and holes, respectively
Implementation Method 3
limitations in conformal deposition processes
Data Source
AI summary
By forming an additional stressed dielectric material after patterning dielectric liners of different intrinsic stress, a significant increase of performance in transistors may be obtained while substantially not contributing to patterning non-uniformities during the formation of respective contact openings in highly scaled semiconductor devices. The additional dielectric layer may be provided with any type of intrinsic stress, irrespective of the previously selected patterning sequence.